公开(公告)号：US08344921B2

公开(公告)日：2013-01-01

申请号：US13072797

申请日：2011-03-28

申请人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

发明人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

IPC分类号： H03M3/00

CPC分类号： H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

摘要： A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.

摘要翻译： Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。

公开(公告)号：US20120112943A1

公开(公告)日：2012-05-10

申请号：US13072797

申请日：2011-03-28

申请人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

发明人： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

IPC分类号： H03M3/02

CPC分类号： H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

摘要： A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.

摘要翻译： Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息，其中截断器的顺序低于积分的顺序。

公开(公告)号：US08890611B2

公开(公告)日：2014-11-18

申请号：US13612784

申请日：2012-09-12

申请人： Hung-Chieh Tsai ,  Chi-Lun Lo ,  Chen-Yen Ho ,  Yu-Hsin Lin

发明人： Hung-Chieh Tsai ,  Chi-Lun Lo ,  Chen-Yen Ho ,  Yu-Hsin Lin

IPC分类号： H03F3/45 ,  H03F3/193 ,  H03F1/14 ,  H03F1/32 ,  H03F3/30

CPC分类号： H03F3/45179 ,  H03F1/14 ,  H03F1/3211 ,  H03F1/483 ,  H03F3/193 ,  H03F3/3023 ,  H03F3/45 ,  H03F3/45076 ,  H03F3/45188 ,  H03F2200/36 ,  H03F2203/45222 ,  H03F2203/45521 ,  H03F2203/45526 ,  H03F2203/45626

摘要： An operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.

摘要翻译： 运算放大器电路包括第一级放大器电路，第二级放大器电路和第一前馈电路。 第一级放大器电路耦合到第一输入节点，用于接收第一输入信号并放大第一输入信号以产生第一放大信号。 第二级放大器电路耦合到第一级放大器电路，用于接收第一放大信号并放大第一放大信号以在第一输出节点产生第一输出信号。 第一前馈电路耦合在第一输入节点和第二级放大器电路之间，用于将第一输入信号向前馈送到第二级放大器电路。

公开(公告)号：US20110181334A1

公开(公告)日：2011-07-28

申请号：US12695164

申请日：2010-01-28

申请人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Chi-Lun Lo ,  Jong-Woei Chen

发明人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Chi-Lun Lo ,  Jong-Woei Chen

IPC分类号： H03L5/00

CPC分类号： H03G3/3052 ,  H03G1/0088

摘要： An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.

摘要翻译： 运算电路包括：增益控制电路，被配置为根据一组控制信号在输入信号上提供增益值，其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器，耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器，其中当所述运算电路运行时，所述第一电容器的第一端始终耦合到 运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。

公开(公告)号：US20090237150A1

公开(公告)日：2009-09-24

申请号：US12051989

申请日：2008-03-20

申请人： Hung-Chieh Tsai ,  Yu-Hsin Lin

发明人： Hung-Chieh Tsai ,  Yu-Hsin Lin

IPC分类号： G05F1/10 ,  H03F3/16

CPC分类号： H03F3/45183 ,  G05F3/30 ,  H03F3/345 ,  H03F2200/456

摘要： A bandgap reference circuit comprising a current mirror, an operational amplifier, first and second BJT transistors is disclosed. The current mirror comprises a first input terminal, a second input terminal and at least one output terminal. The operational amplifier is coupled to the current mirror, wherein a first transistor and a second transistor respectively coupled to the first and the second input terminals have a zero or near zero threshold voltage. The first and second BJT transistors are coupled to two input terminals of the operational amplifier respectively, wherein at least one of the first and second BJT transistors is coupled to the output terminal of the current mirror through a conductive path.

摘要翻译： 公开了一种带隙参考电路，其包括电流镜，运算放大器，第一和第二BJT晶体管。 电流镜包括第一输入端，第二输入端和至少一个输出端。 运算放大器耦合到电流镜，其中分别耦合到第一和第二输入端的第一晶体管和第二晶体管具有零或接近零的阈值电压。 第一和第二BJT晶体管分别耦合到运算放大器的两个输入端，其中第一和第二BJT晶体管中的至少一个通过导电路径耦合到电流镜的输出端。

公开(公告)号：US08638250B2

公开(公告)日：2014-01-28

申请号：US13590491

申请日：2012-08-21

申请人： Chen-Yen Ho ,  Chi-Lun Lo ,  Hung-Chieh Tsai ,  Yu-Hsin Lin

发明人： Chen-Yen Ho ,  Chi-Lun Lo ,  Hung-Chieh Tsai ,  Yu-Hsin Lin

IPC分类号： H03M3/00

CPC分类号： H03F1/0205 ,  H03F3/265 ,  H03F3/30 ,  H03F3/3023 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/18 ,  H03F2203/30021 ,  H03F2203/30033 ,  H03F2203/45022 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03M3/39 ,  H03M3/50

摘要： An amplifier, a fully-differential amplifier and a delta-sigma modulator are disclosed. The disclosed amplifier includes a front-end gain stage, an AC-coupled push-pull output stage and a compensation circuit. The compensation circuit is coupled between the front-end gain stage and an output terminal of the amplifier. The AC-coupled push-pull output stage uses an AC-coupled capacitor (which is a passive two terminal electrical component rather than a stray or parasitic capacitance of a transistor) to couple the front-end gain stage to a gate of a top or bottom transistor of a push-pull structure introduced in the AC-coupled push-pull output stage, and uses a resistance component to couple a gate of the top or bottom transistor (depending on which one is coupled to the AC-coupled capacitor) to a bias voltage level.

摘要翻译： 公开了放大器，全差分放大器和Δ-Σ调制器。 所公开的放大器包括前端增益级，AC耦合推挽输出级和补偿电路。 补偿电路耦合在前端增益级与放大器的输出端之间。 交流耦合推挽输出级使用交流耦合电容器（其是无源双端电气元件而不是晶体管的杂散或寄生电容），以将前端增益级耦合到顶部的栅极或 引入到AC耦合推挽输出级中的推挽结构的底部晶体管，并且使用电阻分量将顶部或底部晶体管的栅极（取决于耦合到AC耦合电容器的栅极）耦合到 偏置电压电平。

公开(公告)号：US08149047B2

公开(公告)日：2012-04-03

申请号：US12051989

申请日：2008-03-20

申请人： Hung-Chieh Tsai ,  Yu-Hsin Lin

发明人： Hung-Chieh Tsai ,  Yu-Hsin Lin

IPC分类号： G05F3/02

CPC分类号： H03F3/45183 ,  G05F3/30 ,  H03F3/345 ,  H03F2200/456

摘要： A bandgap reference circuit comprising a current mirror, an operational amplifier, first and second BJT transistors is disclosed. The current mirror comprises a first input terminal, a second input terminal and at least one output terminal. The operational amplifier is coupled to the current mirror, wherein a first transistor and a second transistor respectively coupled to the first and the second input terminals have a zero or near zero threshold voltage. The first and second BJT transistors are coupled to two input terminals of the operational amplifier respectively, wherein at least one of the first and second BJT transistors is coupled to the output terminal of the current mirror through a conductive path.

摘要翻译： 公开了一种带隙参考电路，其包括电流镜，运算放大器，第一和第二BJT晶体管。 电流镜包括第一输入端，第二输入端和至少一个输出端。 运算放大器耦合到电流镜，其中分别耦合到第一和第二输入端的第一晶体管和第二晶体管具有零或接近零的阈值电压。 第一和第二BJT晶体管分别耦合到运算放大器的两个输入端，其中第一和第二BJT晶体管中的至少一个通过导电路径耦合到电流镜的输出端。

公开(公告)号：US08629712B2

公开(公告)日：2014-01-14

申请号：US13408041

申请日：2012-02-29

申请人： Hung-Chieh Tsai ,  Yu-Hsin Lin

发明人： Hung-Chieh Tsai ,  Yu-Hsin Lin

IPC分类号： G05F3/02

CPC分类号： H03F3/45183 ,  G05F3/30 ,  H03F3/345 ,  H03F2200/456

摘要： An operational amplifier comprises: a plurality of transistors, comprising: a first transistor; and a second transistor, wherein a source of the first transistor is connected to a source of the second transistor; wherein the first transistor and the second transistor have near zero threshold voltage.

摘要翻译： 运算放大器包括：多个晶体管，包括：第一晶体管; 以及第二晶体管，其中所述第一晶体管的源极连接到所述第二晶体管的源极; 其中所述第一晶体管和所述第二晶体管具有接近零阈值电压。

公开(公告)号：US08575970B2

公开(公告)日：2013-11-05

申请号：US12695164

申请日：2010-01-28

申请人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Chi-Lun Lo ,  Jong-Woei Chen

发明人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Chi-Lun Lo ,  Jong-Woei Chen

IPC分类号： H03K17/00

CPC分类号： H03G3/3052 ,  H03G1/0088

摘要： An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.

摘要翻译： 运算电路包括：增益控制电路，被配置为根据一组控制信号在输入信号上提供增益值，其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器，耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器，其中当所述运算电路运行时，所述第一电容器的第一端始终耦合到 运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。

公开(公告)号：US07759977B1

公开(公告)日：2010-07-20

申请号：US12480669

申请日：2009-06-08

申请人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Jong-Woei Chen

发明人： Hung-Chieh Tsai ,  Yu-Hsin Lin ,  Jong-Woei Chen

IPC分类号： H03K19/094

CPC分类号： H03K19/018521

摘要： A buffering circuit includes: a first transistor having a gate terminal coupled to an input signal for buffering the input signal to generate an output signal under an operating current, a second transistor cascoded with the first transistor for generating the operating current for the first transistor according to a control signal at a gate terminal of the second transistor, and a control circuit having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to a reference source. The control circuit adjusts the control signal according to the input signal and the reference source, wherein when a voltage level of the input signal varies, the control circuit is arranged to adjust a voltage level of the control signal such that the adjusted voltage level of the control signal varies inversely proportional to the varied voltage level of the input signal.

摘要翻译： 缓冲电路包括：第一晶体管，其具有耦合到输入信号的栅极端子，用于缓冲输入信号以在工作电流下产生输出信号;与第一晶体管级联的第二晶体管，用于产生用于第一晶体管的工作电流， 涉及在第二晶体管的栅极端子处的控制信号，以及具有耦合到第一晶体管的栅极端子的第一端子和耦合到参考源的第二端子的控制电路。 控制电路根据输入信号和参考源调节控制信号，其中当输入信号的电压电平变化时，控制电路被布置成调节控制信号的电压电平，使得调节的电压电平 控制信号与输入信号的变化电压电平成反比变化。