发明申请
- 专利标题： Generating Hardware Accelerators and Processor Offloads
- 专利标题（中）： 生成硬件加速器和处理器卸载
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申请号： US13358407申请日： 2012-01-25
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公开(公告)号： US20120124588A1公开(公告)日： 2012-05-17
- 发明人: Navendu Sinha , William Charles Jordan , Bryon Irwin Moyer , Stephen John Joseph Fricke , Roberto Attias , Akash Renukadas Deshpande , Vineet Gupta , Shobhit Sonakiya
- 申请人： Navendu Sinha , William Charles Jordan , Bryon Irwin Moyer , Stephen John Joseph Fricke , Roberto Attias , Akash Renukadas Deshpande , Vineet Gupta , Shobhit Sonakiya
- 申请人地址： US CA Mountain View
- 专利权人： SYNOPSYS, INC.
- 当前专利权人： SYNOPSYS, INC.
- 当前专利权人地址： US CA Mountain View
- 主分类号： G06F9/46
- IPC分类号： G06F9/46
摘要：
System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.
公开/授权文献
- US09003166B2 Generating hardware accelerators and processor offloads 公开/授权日：2015-04-07
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