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    Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data
    1.
    发明授权
    Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data 有权
    分组进入/出口块以及用于接收，发送和管理分组化数据的系统和方法

    公开(公告)号：US08289966B1

    公开(公告)日：2012-10-16

    申请号：US11607429

    申请日：2006-12-01

    申请人： Stephen John Joseph Fricke ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

    发明人： Stephen John Joseph Fricke ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

    IPC分类号： G06F13/12 ,  H04L12/28

    CPC分类号： G06F13/385 ,  G06F2213/3808

    摘要： Packet ingress/egress block and logic and system and method for receiving, transmitting, and managing packetized data. System including a line port; a computing resource output port; a host interface; a memory, and a block that: receives information on the line port, creates a context including information for managing computation derived from the received information, and sends context out on computing resource output port. Device comprising first circuit component including line port that receives information, second circuit component that generates context information including an information for managing computation derived from the received unit of information; and third circuit component that communicates the generated context out to a computing resource output port. Method comprising receiving information, generating context information including an information for managing computation derived from the received unit of information; and communicating the generated context information out to an external receiver via a computing resource output port.

    摘要翻译： 分组进入/出口块以及用于接收，发送和管理分组化数据的逻辑和系统和方法。 系统包括线路端口; 计算资源输出端口; 主机接口; 存储器和块，其在线路端口上接收信息，创建包括用于管理从接收到的信息导出的计算的信息的上下文，并且在计算资源输出端口上发送上下文。 包括包含接收信息的线路端口的第一电路组件的设备，产生包括用于管理从所接收的信息单元导出的计算的信息的上下文信息的第二电路组件; 以及将生成的上下文传送到计算资源输出端口的第三电路组件。 一种方法，包括接收信息，产生上下文信息，包括用于管理从接收到的信息单元导出的计算的信息; 以及经由计算资源输出端口将生成的上下文信息传送到外部接收器。

    Generating Hardware Accelerators and Processor Offloads
    2.
    发明申请
    Generating Hardware Accelerators and Processor Offloads 审中-公开
    生成硬件加速器和处理器卸载

    公开(公告)号：US20120124588A1

    公开(公告)日：2012-05-17

    申请号：US13358407

    申请日：2012-01-25

    申请人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    发明人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    IPC分类号： G06F9/46

    CPC分类号： G06F9/5044 ,  G06F9/54

    摘要： System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

    摘要翻译： 用于生成硬件加速器和处理器卸载的系统和方法。 硬件加速系统 用于实现异步卸载的系统和方法。 自动创建硬件加速器的方法 用于从软件程序自动创建用于硬件加速器的测试工具的计算机化方法。 用于互连硬件加速器和处理器的系统和方法。 用于互连处理器和硬件加速器的系统和方法。 计算机实现从软件自动生成硬件加速器的硬件电路逻辑块设计的方法。 存储在有形媒体上的计算机程序和计算机程序产品，其实现本发明的方法和程序。

    Generating hardware accelerators and processor offloads
    3.
    发明授权
    Generating hardware accelerators and processor offloads 有权
    生成硬件加速器和处理器卸载

    公开(公告)号：US08127113B1

    公开(公告)日：2012-02-28

    申请号：US11607452

    申请日：2006-12-01

    申请人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    发明人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    IPC分类号： G06F15/76

    CPC分类号： G06F9/5044 ,  G06F9/54

    摘要： System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

    摘要翻译： 用于生成硬件加速器和处理器卸载的系统和方法。 硬件加速系统 用于实现异步卸载的系统和方法。 自动创建硬件加速器的方法 用于从软件程序自动创建用于硬件加速器的测试工具的计算机化方法。 用于互连硬件加速器和处理器的系统和方法。 用于互连处理器和硬件加速器的系统和方法。 计算机实现从软件自动生成硬件加速器的硬件电路逻辑块设计的方法。 存储在有形媒体上的计算机程序和计算机程序产品，其实现本发明的方法和程序。

    Compounds for modulating integrin CD11b/CD18
    8.
    发明授权
    Compounds for modulating integrin CD11b/CD18 有权
    用于调节整合蛋白CD11b / CD18的化合物

    公开(公告)号：US08846667B2

    公开(公告)日：2014-09-30

    申请号：US13614046

    申请日：2012-09-13

    申请人： Vineet Gupta ,  M. Amin Arnaout

    发明人： Vineet Gupta ,  M. Amin Arnaout

    IPC分类号： A61K31/54 ,  A61K31/425 ,  A61K31/42 ,  A61K31/495

    CPC分类号： G01N33/5032 ,  C07C233/81 ,  C07C251/20 ,  C07C311/39 ,  C07C2601/14 ,  C07D213/85 ,  C07D239/48 ,  C07D249/10 ,  C07D263/46 ,  C07D265/34 ,  C07D277/14 ,  C07D277/36 ,  C07D277/42 ,  C07D277/54 ,  C07D277/72 ,  C07D311/16 ,  C07D333/22 ,  C07D333/68 ,  C07D417/06 ,  C07D417/12 ,  C07D417/14 ,  C07D471/04 ,  C07D471/06 ,  C07D498/04 ,  C07D513/18

    摘要： The application describes an assay for the identification of small molecule modulators of integrin CD11b/CD18 and small molecules capable of modulating activity of this receptor. Such compounds may be used in certain embodiments for treating a disease or condition selected from inflammation, immune-related disorders, cancer, ischemia-reperfusion injury, stroke, neointimal thickening associated with vascular injury, bullous pemphigoid, neonatal obstructive nephropathy, and cardiovascular disease, or in other embodiments for the treatment of a disease or condition selected from immune deficiency, acquired immune deficiency syndrome (AIDS), myeloperoxidase deficiency, Wiskott-Aldrich syndrome, chronic granulomatous disease, hyper-IgM syndromes, leukocyte adhesion deficiency, Chediak-Higashi syndrome, and severe combined immunodeficiency.

    摘要翻译： 该应用描述了用于鉴定整合素CD11b / CD18的小分子调节剂和能够调节该受体活性的小分子的测定法。 这些化合物可用于某些实施方案中用于治疗选自炎症，免疫相关疾病，癌症，缺血再灌注损伤，中风，与血管损伤相关的新内膜增厚，大疱性类天疱疮，新生儿梗阻性肾病和心血管疾病的疾病或病症， 或在其它实施方案中用于治疗选自免疫缺陷，获得性免疫缺陷综合征（AIDS），髓过氧化物酶缺乏症，威斯科特 - 奥德里奇综合征，慢性肉芽肿病，超IgM综合征，白细胞粘附缺陷，Chediak-Higashi综合征 ，和严重的联合免疫缺陷。