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    Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data
    1.
    发明授权
    Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data 有权
    分组进入/出口块以及用于接收，发送和管理分组化数据的系统和方法

    公开(公告)号：US08289966B1

    公开(公告)日：2012-10-16

    申请号：US11607429

    申请日：2006-12-01

    申请人： Stephen John Joseph Fricke ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

    发明人： Stephen John Joseph Fricke ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

    IPC分类号： G06F13/12 ,  H04L12/28

    CPC分类号： G06F13/385 ,  G06F2213/3808

    摘要： Packet ingress/egress block and logic and system and method for receiving, transmitting, and managing packetized data. System including a line port; a computing resource output port; a host interface; a memory, and a block that: receives information on the line port, creates a context including information for managing computation derived from the received information, and sends context out on computing resource output port. Device comprising first circuit component including line port that receives information, second circuit component that generates context information including an information for managing computation derived from the received unit of information; and third circuit component that communicates the generated context out to a computing resource output port. Method comprising receiving information, generating context information including an information for managing computation derived from the received unit of information; and communicating the generated context information out to an external receiver via a computing resource output port.

    摘要翻译： 分组进入/出口块以及用于接收，发送和管理分组化数据的逻辑和系统和方法。 系统包括线路端口; 计算资源输出端口; 主机接口; 存储器和块，其在线路端口上接收信息，创建包括用于管理从接收到的信息导出的计算的信息的上下文，并且在计算资源输出端口上发送上下文。 包括包含接收信息的线路端口的第一电路组件的设备，产生包括用于管理从所接收的信息单元导出的计算的信息的上下文信息的第二电路组件; 以及将生成的上下文传送到计算资源输出端口的第三电路组件。 一种方法，包括接收信息，产生上下文信息，包括用于管理从接收到的信息单元导出的计算的信息; 以及经由计算资源输出端口将生成的上下文信息传送到外部接收器。

    Generating Hardware Accelerators and Processor Offloads
    2.
    发明申请
    Generating Hardware Accelerators and Processor Offloads 审中-公开
    生成硬件加速器和处理器卸载

    公开(公告)号：US20120124588A1

    公开(公告)日：2012-05-17

    申请号：US13358407

    申请日：2012-01-25

    申请人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    发明人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    IPC分类号： G06F9/46

    CPC分类号： G06F9/5044 ,  G06F9/54

    摘要： System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

    摘要翻译： 用于生成硬件加速器和处理器卸载的系统和方法。 硬件加速系统 用于实现异步卸载的系统和方法。 自动创建硬件加速器的方法 用于从软件程序自动创建用于硬件加速器的测试工具的计算机化方法。 用于互连硬件加速器和处理器的系统和方法。 用于互连处理器和硬件加速器的系统和方法。 计算机实现从软件自动生成硬件加速器的硬件电路逻辑块设计的方法。 存储在有形媒体上的计算机程序和计算机程序产品，其实现本发明的方法和程序。

    Generating hardware accelerators and processor offloads
    3.
    发明授权
    Generating hardware accelerators and processor offloads 有权
    生成硬件加速器和处理器卸载

    公开(公告)号：US08127113B1

    公开(公告)日：2012-02-28

    申请号：US11607452

    申请日：2006-12-01

    申请人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    发明人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

    IPC分类号： G06F15/76

    CPC分类号： G06F9/5044 ,  G06F9/54

    摘要： System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

    摘要翻译： 用于生成硬件加速器和处理器卸载的系统和方法。 硬件加速系统 用于实现异步卸载的系统和方法。 自动创建硬件加速器的方法 用于从软件程序自动创建用于硬件加速器的测试工具的计算机化方法。 用于互连硬件加速器和处理器的系统和方法。 用于互连处理器和硬件加速器的系统和方法。 计算机实现从软件自动生成硬件加速器的硬件电路逻辑块设计的方法。 存储在有形媒体上的计算机程序和计算机程序产品，其实现本发明的方法和程序。

    Apparatus, method and computer program for dynamic slip control in real-time scheduling
    4.
    发明授权
    Apparatus, method and computer program for dynamic slip control in real-time scheduling 有权
    实时调度中动态滑移控制的装置，方法和计算机程序

    公开(公告)号：US07805724B1

    公开(公告)日：2010-09-28

    申请号：US10665875

    申请日：2003-09-19

    申请人： Akash Renukadas Deshpande

    发明人： Akash Renukadas Deshpande

    IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F3/00

    CPC分类号： G06F9/4825

    摘要： An apparatus, method, and computer-readable program code for dynamically controlling slip is disclosed. The method monitors the time of an actual interrupt, wakes up, interacts with the physical environment, and then notes the completion time and reduces a wait period. The wait period ends in a scheduled interrupt time. By reducing the wait period based on the difference between the actual interrupt time (instead of the scheduled interrupt time) and the completion time, slip is prevented from accumulating and is reduced.

    摘要翻译： 公开了一种用于动态控制滑移的装置，方法和计算机可读程序代码。 该方法监视实际中断的时间，唤醒，与物理环境交互，然后注意完成时间并减少等待时间。 等待期在预定的中断时间结束。 通过根据实际中断时间（而不是调度的中断时间）与完成时间之间的差减小等待时间，防止滑差积累并减少。