公开(公告)号：US08289966B1

公开(公告)日：2012-10-16

申请号：US11607429

申请日：2006-12-01

申请人： Stephen John Joseph Fricke ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

发明人： Stephen John Joseph Fricke ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

IPC分类号： G06F13/12 ,  H04L12/28

CPC分类号： G06F13/385 ,  G06F2213/3808

摘要： Packet ingress/egress block and logic and system and method for receiving, transmitting, and managing packetized data. System including a line port; a computing resource output port; a host interface; a memory, and a block that: receives information on the line port, creates a context including information for managing computation derived from the received information, and sends context out on computing resource output port. Device comprising first circuit component including line port that receives information, second circuit component that generates context information including an information for managing computation derived from the received unit of information; and third circuit component that communicates the generated context out to a computing resource output port. Method comprising receiving information, generating context information including an information for managing computation derived from the received unit of information; and communicating the generated context information out to an external receiver via a computing resource output port.

摘要翻译： 分组进入/出口块以及用于接收，发送和管理分组化数据的逻辑和系统和方法。 系统包括线路端口; 计算资源输出端口; 主机接口; 存储器和块，其在线路端口上接收信息，创建包括用于管理从接收到的信息导出的计算的信息的上下文，并且在计算资源输出端口上发送上下文。 包括包含接收信息的线路端口的第一电路组件的设备，产生包括用于管理从所接收的信息单元导出的计算的信息的上下文信息的第二电路组件; 以及将生成的上下文传送到计算资源输出端口的第三电路组件。 一种方法，包括接收信息，产生上下文信息，包括用于管理从接收到的信息单元导出的计算的信息; 以及经由计算资源输出端口将生成的上下文信息传送到外部接收器。

公开(公告)号：US20120124588A1

公开(公告)日：2012-05-17

申请号：US13358407

申请日：2012-01-25

申请人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

发明人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

IPC分类号： G06F9/46

CPC分类号： G06F9/5044 ,  G06F9/54

摘要： System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

摘要翻译： 用于生成硬件加速器和处理器卸载的系统和方法。 硬件加速系统 用于实现异步卸载的系统和方法。 自动创建硬件加速器的方法 用于从软件程序自动创建用于硬件加速器的测试工具的计算机化方法。 用于互连硬件加速器和处理器的系统和方法。 用于互连处理器和硬件加速器的系统和方法。 计算机实现从软件自动生成硬件加速器的硬件电路逻辑块设计的方法。 存储在有形媒体上的计算机程序和计算机程序产品，其实现本发明的方法和程序。

公开(公告)号：US08127113B1

公开(公告)日：2012-02-28

申请号：US11607452

申请日：2006-12-01

申请人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

发明人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

IPC分类号： G06F15/76

CPC分类号： G06F9/5044 ,  G06F9/54

摘要： System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

摘要翻译： 用于生成硬件加速器和处理器卸载的系统和方法。 硬件加速系统 用于实现异步卸载的系统和方法。 自动创建硬件加速器的方法 用于从软件程序自动创建用于硬件加速器的测试工具的计算机化方法。 用于互连硬件加速器和处理器的系统和方法。 用于互连处理器和硬件加速器的系统和方法。 计算机实现从软件自动生成硬件加速器的硬件电路逻辑块设计的方法。 存储在有形媒体上的计算机程序和计算机程序产品，其实现本发明的方法和程序。

公开(公告)号：US09003166B2

公开(公告)日：2015-04-07

申请号：US13358407

申请日：2012-01-25

申请人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

发明人： Navendu Sinha ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Roberto Attias ,  Akash Renukadas Deshpande ,  Vineet Gupta ,  Shobhit Sonakiya

IPC分类号： G06F9/30 ,  G06F9/54

CPC分类号： G06F9/5044 ,  G06F9/54

摘要： System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

摘要翻译： 用于生成硬件加速器和处理器卸载的系统和方法。 硬件加速系统 用于实现异步卸载的系统和方法。 自动创建硬件加速器的方法 用于从软件程序自动创建用于硬件加速器的测试工具的计算机化方法。 用于互连硬件加速器和处理器的系统和方法。 用于互连处理器和硬件加速器的系统和方法。 计算机实现从软件自动生成硬件加速器的硬件电路逻辑块设计的方法。 存储在有形媒体上的计算机程序和计算机程序产品，其实现本发明的方法和程序。

公开(公告)号：US08706987B1

公开(公告)日：2014-04-22

申请号：US11607474

申请日：2006-12-01

申请人： Roberto Attias ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

发明人： Roberto Attias ,  William Charles Jordan ,  Bryon Irwin Moyer ,  Stephen John Joseph Fricke ,  Akash Renukadas Deshpande ,  Navendu Sinha ,  Vineet Gupta ,  Shobhit Sonakiya

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/362 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F13/28

摘要： Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.

摘要翻译： 结构化块传输模块，系统架构和传输内容或数据的方法。 允许一个存储器中的内容被移位，移动或复制到另一个存储器而没有来自主机的方向的电路，该电路包括：连接管理器，至少一个复制引擎以及连接管理器和复制引擎之间的连接。 用于将多个源存储器中的一个块的内容传送到多个可能的目的地存储器中的一个的方法，包括：选择源存储器; 选择可用的目的地存储器; 将所选择的目的地标记为不再可用; 将选择的源存储器的内容复制到所选择的目的地存储器中; 并将选定的源标记为可用。

公开(公告)号：US5811987A

公开(公告)日：1998-09-22

申请号：US740948

申请日：1996-11-05

申请人： Benjamin Howard Ashmore, Jr. ,  Jeffery Mark Marshall ,  Bryon Irwin Moyer ,  John David Porter ,  Nicholas A. Schmitz ,  Bradley A. Sharpe-Geisler

发明人： Benjamin Howard Ashmore, Jr. ,  Jeffery Mark Marshall ,  Bryon Irwin Moyer ,  John David Porter ,  Nicholas A. Schmitz ,  Bradley A. Sharpe-Geisler

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K19/173 ,  H03K19/177 ,  H03K19/21 ,  H03K7/38

CPC分类号： H03K3/037 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17772 ,  H03K19/215 ,  H03K3/0375 ,  H03K3/356156

摘要： A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.

摘要翻译： 复合非常高密度可编程逻辑器件中的可编程逻辑块的块时钟和初始化电路为可编程逻辑块中的元件生成多个块时钟信号和块初始化信号。 块时钟和初始化电路包括块时钟发生器电路和块初始化电路。 块时钟发生器电路以多个乘积项和多个时钟信号作为输入信号接收第一组乘积项。 响应于输入信号，块时钟发生器电路在多个块时钟线上产生输出信号。 块初始化电路接收多个乘积项中的第二组乘积项作为输入信号。 响应于输入信号，块初始化电路在块初始化线上产生多个输出信号。