发明申请
US20120146146A1 PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE
有权
具有门控电压（Vt）的栅极 - 体积隧道电流区域（DP）半导体绝缘体（SOI）场效应晶体管（FET）结构和形成结构的方法
- 专利标题： PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE
- 专利标题（中）： 具有门控电压（Vt）的栅极 - 体积隧道电流区域（DP）半导体绝缘体（SOI）场效应晶体管（FET）结构和形成结构的方法
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申请号： US12967329申请日： 2010-12-14
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公开(公告)号： US20120146146A1公开(公告)日： 2012-06-14
- 发明人: Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
- 申请人： Brent A. Anderson , Andres Bryant , Jiale Liang , Edward J. Nowak
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/336
摘要：
Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.