Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure
    1.
    发明授权
    Partially depleted (PD) semiconductor-on-insulator (SOI) field effect transistor (FET) structure with a gate-to-body tunnel current region for threshold voltage (VT) lowering and method of forming the structure 有权
    部分耗尽(PD)绝缘体上半导体(SOI)场效应晶体管(FET)结构,具有用于阈值电压(VT)降低的栅 - 体隧道电流区域和形成结构的方法

    公开(公告)号:US08698245B2

    公开(公告)日:2014-04-15

    申请号:US12967329

    申请日:2010-12-14

    IPC分类号: H01L27/12

    摘要: Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

    摘要翻译: 公开了具有栅对体隧道电流区域(GTBTCR)的场效应晶体管的实施例和方法。 在一个实施例中,具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分,以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。 在另一个实施例中,半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括:与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。 具有第二导电类型的栅极穿过中心部分。

    PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE
    2.
    发明申请
    PARTIALLY DEPELETED (DP) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (Vt) LOWERING AND METHOD OF FORMING THE STRUCTURE 有权
    具有门控电压(Vt)的栅极 - 体积隧道电流区域(DP)半导体绝缘体(SOI)场效应晶体管(FET)结构和形成结构的方法

    公开(公告)号:US20120146146A1

    公开(公告)日:2012-06-14

    申请号:US12967329

    申请日:2010-12-14

    IPC分类号: H01L29/78 H01L21/336

    摘要: Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

    摘要翻译: 公开了具有栅对体隧道电流区域(GTBTCR)的场效应晶体管的实施例和方法。 在一个实施例中,具有不同导电类型的相邻部分的栅极穿过半导体层的中心部分,以在中心部分内分别在具有不同导电类型的相邻部分之下分别形成沟道区域和GTBTCR。 在另一个实施例中,半导体层具有具有沟道区域的中心部分和GTBTCR。 GTBTCR包括:与沟道区相邻并掺杂相同的第一导电类型掺杂剂的较高浓度的第一注入区; 具有第二导电类型的与第一植入区相邻的第二植入区; 以及植入区域之间的增强的生成和重组区域。 具有第二导电类型的栅极穿过中心部分。