公开(公告)号：US09768304B2

公开(公告)日：2017-09-19

申请号：US13492108

申请日：2012-06-08

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L21/20 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10 ,  H01L21/3115 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/31155 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

公开(公告)号：US09114114B2

公开(公告)日：2015-08-25

申请号：US11766224

申请日：2007-06-21

申请人： Brent A. Anderson ,  John M. Kaiser ,  Ilene K. Cooper ,  David J. Hausman ,  Barry D. Glazier ,  Jacqueline B. Kramer ,  Tracey L. Knapp

发明人： Brent A. Anderson ,  John M. Kaiser ,  Ilene K. Cooper ,  David J. Hausman ,  Barry D. Glazier ,  Jacqueline B. Kramer ,  Tracey L. Knapp

IPC分类号： A61K36/185 ,  A21D13/08 ,  A23G1/32 ,  A23G1/46 ,  A23G1/56 ,  A23G3/48 ,  A23L1/164 ,  A23L1/30 ,  A23L1/38

CPC分类号： A61K36/185 ,  A21D13/80 ,  A23G1/32 ,  A23G1/46 ,  A23G1/52 ,  A23G1/56 ,  A23G3/48 ,  A23L5/00 ,  A23L7/00 ,  A23L7/126 ,  A23L9/00 ,  A23L25/10 ,  A23L29/30 ,  A23L33/105 ,  A23L33/125 ,  A23V2002/00 ,  A61K31/353 ,  A23V2250/2132

摘要： Milling dry extracts containing cocoa polyphenols (CPs) to reduce the particle size improves the flavor of edible products (e.g., foods, medical foods, nutritional supplements, and pharmaceuticals) or additives containing the milled cocoa extracts. The products, e.g., chocolates, are less astringent and less bitter. The mean particle size after milling is less than about 15 microns, preferably less than about 10 microns, and most preferably less than about 5 microns. The total CP content of the milled extracts is at least about 300 milligrams and preferably about 300 to about 700 milligrams per gram of milled extract. The additives consist essentially of (i) the milled high CP cocoa extract and (ii) a fat (e.g., cocoa butter), an oil (e.g., vegetable oil), or a syrup (e.g., corn syrup).

摘要翻译： 含有可可多元酚（CP）的干燥提取物的研磨以减小颗粒尺寸，改善了可食用产品（例如食品，医疗食品，营养补充剂和药物）或含有研磨的可可提取物的添加剂的风味。 产品，例如巧克力，涩味少，苦味少。 研磨后的平均粒度小于约15微米，优选小于约10微米，最优选小于约5微米。 研磨的提取物的总CP含量为每克研磨提取物至少约300毫克，优选约300至约700毫克。 添加剂基本上由（i）研磨的高CP可可提取物和（ii）脂肪（例如可可脂），油（例如植物油）或糖浆（例如玉米糖浆）组成。

公开(公告)号：US08962398B2

公开(公告)日：2015-02-24

申请号：US13454518

申请日：2012-04-24

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7841 ,  H01L29/66795 ,  H01L29/785

摘要： A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.

公开(公告)号：US08941180B2

公开(公告)日：2015-01-27

申请号：US13044872

申请日：2011-03-10

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L27/02 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/78624

摘要： Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin).

摘要翻译： 公开了具有不对称FET作为电子电路的功率门的集成电路，其具有至少两个堆叠的对称场效应晶体管。 非对称FET具有不对称的卤素配置（即，具有比漏极侧卤素更高的掺杂剂浓度的单个源极卤素或源极卤素）和非对称源极/漏极延伸配置（即，源极延伸可以 通过栅极结构比漏极延伸更大程度地重叠和/或源极延伸可以具有比漏极延伸更高的掺杂剂浓度）。 结果，不对称FET具有低截止电流。 在操作中，当电子电路处于待机状态时，不对称FET被关闭，并且由于低关断电流（Ioff），有效地减少了来自电子电路的待机漏电流。 另外，避免使用电子电路内的层叠的非对称场效应晶体管本身可以防止由于线性漏极电流（Idlin）的降低导致的性能劣化。

公开(公告)号：US08900954B2

公开(公告)日：2014-12-02

申请号：US13289051

申请日：2011-11-04

申请人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

CPC分类号： H01L29/1041 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28026 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78

摘要： A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

摘要翻译： 一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口 。 保形介电层覆盖衬底的沟道区。 该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。 此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

公开(公告)号：US08557647B2

公开(公告)日：2013-10-15

申请号：US13229154

申请日：2011-09-09

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/335 ,  H01L21/8232 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/00

CPC分类号： H01L29/6653 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/785

摘要： A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material.

摘要翻译： 在衬底上形成特征的方法包括在衬底上形成至少一层特征材料，在特征材料的至少一层上图案化光刻抗蚀剂材料，去除特征材料的部分以限定特征，沉积 在抗蚀剂材料上的掩模材料层和衬底的暴露区域，修改衬底的一部分，以及去除掩模材料层和抗蚀剂材料。

公开(公告)号：US08546252B2

公开(公告)日：2013-10-01

申请号：US12573440

申请日：2009-10-05

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L29/72

CPC分类号： H01L29/4983 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

摘要翻译： 一种用于产生具有降低的阈值电压滚降的金属栅极的结构和方法。 一种方法包括：在衬底上形成栅极电介质材料; 在所述栅极电介质材料上形成栅电极材料; 以及改变栅电极材料的第一部分。 改变导致栅电极材料的第一部分具有不同于与栅电极材料的第二部分相关联的第二功函数的第一功函数。

公开(公告)号：US08524546B2

公开(公告)日：2013-09-03

申请号：US12909919

申请日：2010-10-22

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/84 ,  H01L21/336 ,  H01L27/088

CPC分类号： H01L29/7831 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

摘要： A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The gate conductor is positioned adjacent to a relatively larger portion of the sides of the second rectangular fin structure and is positioned adjacent to a relatively smaller portion of the sides of the first rectangular fin structure.

公开(公告)号：US08518611B2

公开(公告)日：2013-08-27

申请号：US13007242

申请日：2011-01-14

申请人： Brent A. Anderson ,  Jeb H. Rankin ,  Adam C. Smith

发明人： Brent A. Anderson ,  Jeb H. Rankin ,  Adam C. Smith

IPC分类号： G03F1/68

CPC分类号： G03F7/203 ,  G03F1/68

摘要： A mask fabrication method can include receiving a mask design, sending first exposure parameters to a first exposure machine, sending second exposure parameters to a second exposure machine, sending a first exposure generation command to the first machine based on the first exposure parameters and sending a second exposure generation command to the second machine based on the second exposure parameters.

摘要翻译： 掩模制造方法可以包括接收掩模设计，将第一曝光参数发送到第一曝光机，向第二曝光机发送第二曝光参数，基于第一曝光参数向第一机器发送第一曝光生成命令，并发送 基于第二曝光参数向第二机器提供第二曝光生成命令。

公开(公告)号：US08507962B2

公开(公告)日：2013-08-13

申请号：US12897230

申请日：2010-10-04

申请人： Brent A. Anderson ,  Mark D. Jaffe

发明人： Brent A. Anderson ,  Mark D. Jaffe

IPC分类号： H01L31/062

CPC分类号： H01L27/14603 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14689

摘要： Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.

摘要翻译： 像素传感器单元，例如CMOS光学成像器，制造和设计结构的方法被提供有防止载流子漂移到扩散区域的隔离结构。 像素传感器单元包括感光区域和与感光区域相邻的栅极。 像素传感器单元还包括与栅极相邻的扩散区域。 像素传感器单元还包括位于栅极的沟道区域周围和感光区域下方的隔离区域，其防止在光敏区域中收集的电子漂移到扩散区域。