发明申请
US20120322259A1 DEFECT FREE DEEP TRENCH METHOD FOR SEMICONDUCTOR CHIP 有权
用于半导体芯片的缺陷自由深度方法

  • 专利标题: DEFECT FREE DEEP TRENCH METHOD FOR SEMICONDUCTOR CHIP
  • 专利标题(中): 用于半导体芯片的缺陷自由深度方法
  • 申请号: US13162873
    申请日: 2011-06-17
  • 公开(公告)号: US20120322259A1
    公开(公告)日: 2012-12-20
  • 发明人: Kun-Yi Liu
  • 申请人: Kun-Yi Liu
  • 主分类号: H01L21/28
  • IPC分类号: H01L21/28 H01L21/311
DEFECT FREE DEEP TRENCH METHOD FOR SEMICONDUCTOR CHIP
摘要:
A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.
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