公开(公告)号：US07659965B2

公开(公告)日：2010-02-09

申请号：US11544417

申请日：2006-10-06

申请人： Kun-Yi Liu

发明人： Kun-Yi Liu

IPC分类号： G03B27/58 ,  G03B27/42 ,  G03B27/72 ,  G03B27/32

CPC分类号： G03F7/707 ,  G03F9/708 ,  G03F9/7084

摘要： An optical lithography exposure apparatus which may be a stepper or a scanner, provides a wafer chuck that retains a wafer and at least one opaque exposure shield that extends over a discrete peripheral edge portion of the wafer thereby preventing illumination from exposing the portion of the wafer beneath the exposure shield. In a positive photoresist system, the portions of the wafer blocked from exposure by the shields, include alignment marks and the unexposed photoresist remains over the alignment marks thereby protecting the alignment marks from destruction or damage during subsequent patterning operations used to form patterns in the film being patterned.

摘要翻译： 可以是步进器或扫描仪的光学曝光设备提供保持晶片的晶片卡盘和在晶片的离散外围边缘部分上延伸的至少一个不透明曝光屏蔽，从而防止照射暴露晶片的该部分 曝光盾下方。 在正光致抗蚀剂系统中，晶片被屏蔽物遮挡的部分包括对准标记，并且未曝光的光致抗蚀剂保留在对准标记上，从而保护对准标记免于在用于在膜中形成图案的后续图案化操作期间的破坏或损坏 被图案化

公开(公告)号：US08951833B2

公开(公告)日：2015-02-10

申请号：US13162873

申请日：2011-06-17

申请人： Kun-Yi Liu

发明人： Kun-Yi Liu

IPC分类号： H01L21/00 ,  H01L21/311 ,  B81C1/00 ,  H01L23/58 ,  H01L21/28 ,  H01L21/50 ,  H01L21/304

CPC分类号： B81C1/00063 ,  B81B2207/012 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/00

摘要： A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.

摘要翻译： 在半导体集成电路芯片上形成大的基本上无缺陷的空隙区域的方法包括通过钝化层处理操作来处理芯片，然后在单独的专用蚀刻操作中在集成电路芯片的指定空白区域中形成一个或多个开口。 一个或多个开口可以构成半导体芯片的总面积的5-10％或更多。 空隙区域是深沟槽开口，其在一个实施例中延伸穿过钝化层以及通过露出衬底表面的空白区域中的所有其它材料层，并且穿过除了在另一个中直接形成在衬底上的场氧化物层之外的所有材料层 实施例。

公开(公告)号：US20080084550A1

公开(公告)日：2008-04-10

申请号：US11544417

申请日：2006-10-06

申请人： Kun-Yi Liu

发明人： Kun-Yi Liu

IPC分类号： G03F7/20 ,  G03B27/58

CPC分类号： G03F7/707 ,  G03F9/708 ,  G03F9/7084

摘要： An optical lithography exposure apparatus which may be a stepper or a scanner, provides a wafer chuck that retains a wafer and at least one opaque exposure shield that extends over a discrete peripheral edge portion of the wafer thereby preventing illumination from exposing the portion of the wafer beneath the exposure shield. In a positive photoresist system, the portions of the wafer blocked from exposure by the shields, include alignment marks and the unexposed photoresist remains over the alignment marks thereby protecting the alignment marks from destruction or damage during subsequent patterning operations used to form patterns in the film being patterned.

摘要翻译： 可以是步进器或扫描仪的光学曝光设备提供保持晶片的晶片卡盘和在晶片的离散外围边缘部分上延伸的至少一个不透明曝光屏蔽，从而防止照射暴露晶片的该部分 曝光盾下方。 在正光致抗蚀剂系统中，晶片被屏蔽物遮挡的部分包括对准标记，并且未曝光的光致抗蚀剂保留在对准标记上，从而保护对准标记免于在用于在膜中形成图案的后续图案化操作期间的破坏或损坏 被图案化

公开(公告)号：US6030732A

公开(公告)日：2000-02-29

申请号：US226276

申请日：1999-01-07

申请人： Kun-Yi Liu

发明人： Kun-Yi Liu

IPC分类号： G03F7/16 ,  H01L21/027 ,  G03F9/00 ,  H01L21/306

CPC分类号： H01L21/0274 ,  G03F7/16

摘要： During the course of manufacturing an IC, the thickness of the photoresist layer varies. In the presence of multiple steps, the difference between the maximum photoresist thickness and the minimum thickness can be quite substantial. It is sometimes the case that the minimum thickness is insufficient in some spots for proper exposure of the resist to be possible. The presence of such spots is detected by means of a monitor in the form of an optical mask comprising a group of lines whose width is close to the critical dimension together with an isolated line of similar width and a second, wider, isolated line. A photoresist image of the process monitor is formed in the kerf for each of the layers that is deposited, with the mask being shifted by about half its length between successive depositions. This ensures that a step is formed between successive layers so that if the photoresist layer is too thin at some point this will be reflected in the monitor. By measuring the widths of lines in the monitor, both in the photoresist image and in the subsequent etched image, the presence of regions where the photoresist is of less than adequate thickness can be inferred from the narrowing of the lines relative to their widths in the original optical monitor mask.

摘要翻译： 在制造IC的过程中，光致抗蚀剂层的厚度变化。 在存在多个步骤的情况下，最大光致抗蚀剂厚度和最小厚度之间的差异可能相当大。 有时在一些点上最小厚度不足以适当地曝光抗蚀剂是可能的。 通过以光学掩模的形式的监视器来检测这种斑点的存在，所述监视器包括宽度接近临界尺寸的一组线以及类似宽度的隔离线和第二，更宽的隔离线。 在沉积的每个层的切口中形成过程监视器的光致抗蚀剂图像，其中掩模在连续沉积之间移动大约一半的长度。 这确保了在连续层之间形成台阶，使得如果在某一点光致抗蚀剂层太薄，则这将在监视器中反映出来。 通过测量监测器中的线的宽度，在光致抗蚀剂图像和随后的蚀刻图像中，光致抗蚀剂的厚度小于足够的区域的存在可以从线的变窄相对于其在 原装光学显示器面罩。

公开(公告)号：US20120322259A1

公开(公告)日：2012-12-20

申请号：US13162873

申请日：2011-06-17

申请人： Kun-Yi Liu

发明人： Kun-Yi Liu

IPC分类号： H01L21/28 ,  H01L21/311

CPC分类号： B81C1/00063 ,  B81B2207/012 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/00

摘要： A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.

摘要翻译： 在半导体集成电路芯片上形成大的基本上无缺陷的空隙区域的方法包括通过钝化层处理操作来处理芯片，然后在单独的专用蚀刻操作中在集成电路芯片的指定空白区域中形成一个或多个开口。 一个或多个开口可以构成半导体芯片的总面积的5-10％或更多。 空隙区域是深沟槽开口，其在一个实施例中延伸穿过钝化层以及通过露出衬底表面的空白区域中的所有其它材料层，并且穿过除了在另一个中直接形成在衬底上的场氧化物层之外的所有材料层 实施例。

公开(公告)号：US07489982B2

公开(公告)日：2009-02-10

申请号：US11521871

申请日：2006-09-15

申请人： Kun-Yi Liu ,  Dean Yi Liu

发明人： Kun-Yi Liu ,  Dean Yi Liu

IPC分类号： G06F19/00

CPC分类号： G03F7/26 ,  G03F7/70508 ,  G03F7/70525

摘要： A method and a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded when a wafer is processed and transferred during lithography operations. The data is parsed and saved into an MES database. A report server accesses the database responsive to a query made of the database. A query may specify one or more fabrication parameters. The specified fabrication parameter or parameters is fixed and a data display is provided that compares times for processing and transferring wafers in various lithography operations used in the production of the semiconductor device and bottlenecks in lithography operations are identified by the comparative data.

摘要翻译： 一种方法和计算机可读介质包括用于获得编程到处理配方中的时间数据或者在光刻操作期间晶片被处理和传送时记录的指令。 数据被解析并保存到MES数据库中。 报表服务器响应于对数据库的查询而访问数据库。 查询可以指定一个或多个制造参数。 指定的制造参数或参数是固定的，并且提供了数据显示，其比较了用于在半导体器件的生产中使用的各种光刻操作中处理和转移晶片的时间，并且通过比较数据来识别光刻操作中的瓶颈。

公开(公告)号：US06664177B1

公开(公告)日：2003-12-16

申请号：US10062645

申请日：2002-02-01

申请人： Kwang-Ming Lin ,  Chung-Hung Lu ,  Szu-An Wu ,  Ya-Li Tai ,  Kun-Yi Liu

发明人： Kwang-Ming Lin ,  Chung-Hung Lu ,  Szu-An Wu ,  Ya-Li Tai ,  Kun-Yi Liu

IPC分类号： H01L214763

CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/76807

摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, to improve the photolithography processing window of a multi-layered dual damascene process by using a dielectric anti-reflective coating, DARC, comprised of multiple layers of silicon oxynitride, SiON, with varying k, dielectric constant values and thickness, to reduce reflectivity and improve light absorption. By varying both the thickness and the dielectric constant of the layers, the optical properties of light absorption, refractive indices, and light reflection are optimized.

摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及通过使用由多层硅构成的介电抗反射涂层DARC来改进多层双镶嵌工艺的光刻处理窗口 氧氮化物，SiON，具有不同的k，介电常数值和厚度，以减少反射率并改善光吸收。 通过改变层的厚度和介电常数，优化光吸收，折射率和光反射的光学性质。

公开(公告)号：US06602642B2

公开(公告)日：2003-08-05

申请号：US09941538

申请日：2001-08-29

申请人： Kun-Yi Liu ,  Chin-Chuan Hsieh ,  Ching-Ming Chen

发明人： Kun-Yi Liu ,  Chin-Chuan Hsieh ,  Ching-Ming Chen

IPC分类号： G03F900

CPC分类号： G03F1/36 ,  G03F1/44 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/70591 ,  G06K7/0095

摘要： An optical proximity correction (OPC) verification mask is disclosed. The mask includes device areas that are separated by scribe lines. One or more OPC test patterns are integrated into the scribe lines for verification purposes. These patterns can include: line-end shortening (LES) patterns, such as serifs and hammerheads added to the ends of lines; corner rounding patterns, such as positive and negative serifs; and, scattering bars (SB's) and anti-scattering bars (ASB's) to compensate for isolated-dense proximity effects and isolated-feature depth of focus reduction. Other OPC patterns may also be included. A method for making the mask, and a semiconductor device created at least in part by a method including use of the mask, are also disclosed.

摘要翻译： 公开了一种光学邻近校正（OPC）验证掩模。 掩模包括由划线分开的设备区域。 为了验证目的，将一个或多个OPC测试图案集成到划线中。 这些图案可以包括：线端缩短（LES）图案，如线条和锤头添加到线的末端; 角圆形图案，如正面和负面衬线; 和散射棒（SB）和防散射棒（ASB），以补偿孤立密集邻近效应和孤立特征聚焦减少深度。 也可以包括其他OPC模式。 还公开了制造掩模的方法，以及至少部分地通过包括使用掩模的方法产生的半导体器件。

公开(公告)号：US06602641B1

公开(公告)日：2003-08-05

申请号：US09837598

申请日：2001-04-19

申请人： Kun Yi Liu

发明人： Kun Yi Liu

IPC分类号： G03F900

CPC分类号： G03F7/70633 ,  G03F9/7076

摘要： A new method is provided for the use of alignment marks. In prior art methods, a combination mask is mounted in a mask holder. The combination mask contains multiple, different alignment marks for different purposes and steps in a semiconductor processing sequence. This mark is printed onto the surface of a wafer. Using the method of the invention, a reticle is used that does not contain any patterns (a zero-layer reticle), on this zero-layer reticle an alignment mark is created. This zero-layer alignment mark is referred to as the zero-mark alignment mark, this alignment mark can be printed directly onto the wafer surface. Under the invention, the zero-layer reticle takes the place of the prior art mask holder, on the zero-layer reticle an alignment mark is created that can be directly printed from the zero-layer reticle onto the surface of a wafer. The zero-layer reticle further contains a multiplicity of production alignment marks in a location that is fixed with respect to the alignment mark. The location of the alignment marks therefore corresponds to a location of each alignment mark that belongs to the multiplicity of production alignment marks.

摘要翻译： 提供了一种新的对准标记的使用方法。 在现有技术的方法中，将组合掩模安装在掩模支架中。 组合掩模包含用于不同目的的多个不同对准标记和半导体处理序列中的步骤。 该标记被印刷到晶片的表面上。 使用本发明的方法，使用不包含任何图案（零层掩模版）的掩模版，在该零层掩模版上产生对准标记。 该零层对准标记被称为零标记对准标记，该对准标记可以直接印刷到晶片表面上。 在本发明下，零层掩模版代替现有技术的掩模支架，在零层掩模版上产生可以从零层掩模版直接印刷到晶片表面上的对准标记。 零层掩模版在相对于对准标记固定的位置中还包含多个生产对准标记。 因此，对准标记的位置对应于属于多个生产对准标记的每个对准标记的位置。

公开(公告)号：US20080071405A1

公开(公告)日：2008-03-20

申请号：US11521871

申请日：2006-09-15

申请人： Kun-Yi Liu ,  Dean Yi Liu

发明人： Kun-Yi Liu ,  Dean Yi Liu

IPC分类号： G06F19/00

CPC分类号： G03F7/26 ,  G03F7/70508 ,  G03F7/70525

摘要： A method and a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded when a wafer is processed and transferred during lithography operations. The data is parsed and saved into an MES database. A report server accesses the database responsive to a query made of the database. A query may specify one or more fabrication parameters. The specified fabrication parameter or parameters is fixed and a data display is provided that compares times for processing and transferring wafers in various lithography operations used in the production of the semiconductor device and bottlenecks in lithography operations are identified by the comparative data.

摘要翻译： 一种方法和计算机可读介质包括用于获得编程到处理配方中的时间数据或者在光刻操作期间晶片被处理和传送时记录的指令。 数据被解析并保存到MES数据库中。 报表服务器响应于对数据库的查询而访问数据库。 查询可以指定一个或多个制造参数。 指定的制造参数或参数是固定的，并且提供了数据显示，其比较了用于半导体器件生产中使用的各种光刻操作中的晶片的处理和转移的时间，并且通过比较数据来识别光刻操作中的瓶颈。