Invention Application
- Patent Title: SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Application No.: US13583409Application Date: 2011-03-09
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Publication No.: US20130043537A1Publication Date: 2013-02-21
- Inventor: Yasuo Arai , Masao Okihara , Hiroki Kasai
- Applicant: Yasuo Arai , Masao Okihara , Hiroki Kasai
- Applicant Address: JP Tokyo JP Ibaraki
- Assignee: LAPIS Semiconductor Co., Ltd.,INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
- Current Assignee: LAPIS Semiconductor Co., Ltd.,INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
- Current Assignee Address: JP Tokyo JP Ibaraki
- Priority: JP2012-052173 20100309
- International Application: PCT/JP2011/055546 WO 20110309
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/336

Abstract:
There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
Public/Granted literature
- US08963246B2 Semiconductor device and method for manufacturing semiconductor device Public/Granted day:2015-02-24
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