公开(公告)号：US08928101B2

公开(公告)日：2015-01-06

申请号：US13253791

申请日：2011-10-05

Applicant: Hiroki Kasai ,  Yasuo Arai ,  Takaki Hatsui

Inventor： Hiroki Kasai ,  Yasuo Arai ,  Takaki Hatsui

IPC: H01L31/0224 ,  H01L27/146 ,  H01L27/12

CPC classification number: H01L27/14607 ,  H01L27/1203 ,  H01L27/14659

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; an insulation layer on the first semiconductor layer; a second semiconductor layer in the insulation layer; an active element in the second semiconductor layer; a first semiconductor region on the first semiconductor layer and of a second conductivity type; a second semiconductor region in the first semiconductor region and of the second conductivity type with a higher impurity concentration than the first semiconductor region; a first conductor in a through hole in the insulation layer and connected to the second semiconductor region; a second conductor above or within the insulation layer, the second conductor surrounding the first conductor such that an outside edge thereof is outside the second semiconductor region; a third conductor connecting the first and second conductors; and a fourth conductor connected to the first semiconductor layer.

Abstract translation: 半导体器件包括：第一导电类型的第一半导体层; 第一半导体层上的绝缘层; 绝缘层中的第二半导体层; 第二半导体层中的有源元件; 第一半导体区域和第二导电类型的第一半导体区域; 在第一半导体区域中的第二半导体区域和具有比第一半导体区域更高的杂质浓度的第二导电类型的第二半导体区域; 绝缘层中的通孔中的第一导体，并连接到第二半导体区; 绝缘层之上或之内的第二导体，所述第二导体围绕所述第一导体，使得其外边缘在所述第二半导体区域的外部; 连接第一和第二导体的第三导体; 以及连接到第一半导体层的第四导体。

公开(公告)号：US20130043537A1

公开(公告)日：2013-02-21

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

公开(公告)号：US5349669A

公开(公告)日：1994-09-20

申请号：US12618

申请日：1993-02-02

Applicant: Yasuo Arai ,  Hisatake Sato

Inventor： Yasuo Arai ,  Hisatake Sato

IPC: G06F1/30 ,  G06F11/00 ,  G06F11/14 ,  G11C7/22 ,  G06F12/16

CPC classification number: G06F11/0754 ,  G06F1/30 ,  G06F11/004 ,  G11C7/22 ,  G06F11/0757 ,  G06F11/1415

Abstract: The present invention relates to a data protection (310) for preventing data from being erroneously written in a data holding circuit (307). A data protection circuit (311) receives a data protection set release select signal Sa provided by a processor (330), thereby causing a second timer (316) to start timing. The data protection circuit (311) further detects the level of a chip select signal CS provided by a power supply monitoring circuit (320) after the second timer (316) timed the time interval T2 and provides a data protection signal DP corresponding to the signal Sa to the data holding circuit (307) only in the case that the data protection circuit (311) judged that the main power supply (305) is at normal state.

Abstract translation: 本发明涉及一种用于防止数据被错误写入数据保持电路（307）的数据保护（310）。 数据保护电路（311）接收由处理器（330）提供的数据保护设置释放选择信号Sa，从而使第二定时器（316）开始定时。 数据保护电路（311）在第二定时器（316）定时到时间间隔T2之后，进一步检测由电源监视电路（320）提供的片选信号CS的电平，并提供对应于信号的数据保护信号DP 只有在数据保护电路（311）判断主电源（305）处于正常状态的情况下，才将数据保持电路Sa连接到数据保持电路（307）。

公开(公告)号：US5502418A

公开(公告)日：1996-03-26

申请号：US380580

申请日：1995-01-30

Applicant: Yasuo Arai

Inventor： Yasuo Arai

IPC: H03K3/354 ,  H03K3/03 ,  H03L7/099 ,  H03B5/24 ,  H03K3/353

CPC classification number: H03L7/0995 ,  H03K3/0315

Abstract: The present invention provides a voltage controlled oscillating circuit comprising a multi-staged phase inversion circuit composed of 4 or more even-number stages of phase inversion devices connected in series; and a switch circuit having a delay time characteristic similar to that of said phase inversion circuit, wherein the switch circuit satisfies oscillation conditions by converting an output phase of the even-numbered inverters connected in series into a phase that is the same as those of the outputs of odd-numbered inverters connected in series; thereby obtaining timing signals having a period equal to 1/N of the oscillation period.

Abstract translation: 本发明提供了一种压控振荡电路，包括由串联连接的4个或更多个偶数阶段的相位反相装置构成的多级相位反转电路; 以及具有与所述相位反转电路类似的延迟时间特性的开关电路，其中所述开关电路通过将串联连接的所述偶数反相器的输出相位转换成与所述相位相同的相位来满足振荡条件 串联连接的奇数型逆变器的输出; 从而获得周期等于振荡周期的1 / N的定时信号。

公开(公告)号：US4812169A

公开(公告)日：1989-03-14

申请号：US60939

申请日：1987-06-09

Applicant: Sadaji Matsuura ,  Yasuo Arai ,  Shigeki Aoki ,  Satoru Ando

Inventor： Sadaji Matsuura ,  Yasuo Arai ,  Shigeki Aoki ,  Satoru Ando

IPC: C04B28/00 ,  C04B30/00 ,  C09D5/14

CPC classification number: C04B28/00 ,  C04B30/00 ,  Y02W30/92

Abstract: A fire-resistant, light weight construction material is prepared by subjecting fly ash and/or paper sludge incineration ash to a swelling treatment with a mineral acid to prepare a slurry; and kneading, shaping and hardening the slurry.

公开(公告)号：US4660608A

公开(公告)日：1987-04-28

申请号：US786309

申请日：1985-10-10

Applicant: Yasuo Arai

Inventor： Yasuo Arai

IPC: A61K8/00 ,  A45D33/00 ,  A45D40/16 ,  A61K8/90 ,  A61Q1/00 ,  A61Q1/02 ,  B30B9/06 ,  B65B1/26 ,  B65B1/24

CPC classification number: B30B15/302 ,  A45D33/006 ,  A45D40/16 ,  B30B15/0017 ,  B30B9/06

Abstract: Loading and solidifying of a cosmetic material is achieved by dripping a viscous cosmetic material into a container having a filter bottom, interposing a liquid absorbent membrance between the container and a presser, compressing the cosmetic material by the presser with the membrance interposed therebetween, and squeezing a solvent from the cosmetic material through the filter during such compression. A supporting block holds the container in position for it to be subjected to vacuum suction. The presser includes inner and outer pressing blocks and drives for moving the pressing blocks. The inner block is capable of fitting into the container to compress the cosmetic material, while the outer block abuts against the upper rim of the container.

Abstract translation: 通过将粘性化妆品滴入具有过滤器底部的容器中，在容器和压力机之间插入液体吸收膜，通过压片机将化妆品材料压在其间并将其挤压，从而实现化妆品的加载和固化 在这种压缩期间来自化妆品材料通过过滤器的溶剂。 支撑块将容器保持就位以使其经受真空吸力。 压脚包括用于移动按压块的内部和外部按压块和驱动器。 内部块能够装配到容器中以压缩化妆品材料，而外部块抵靠容器的上边缘。

公开(公告)号：US08963246B2

公开(公告)日：2015-02-24

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/144 ,  H01L29/861 ,  H01L29/786

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract translation: 提供了半导体器件和半导体器件的制造方法。 在由高电阻N型衬底形成的N型半导体层内，形成P型阱扩散层和P型提取层，并将其固定为接地电位。 由此，在P型阱扩散层侧扩散的耗尽层未达到P型阱扩散层与埋入氧化膜之间的层间界限。 因此，P型阱扩散层的表面周围的电位保持在接地电位。 因此，当将电压施加到N型半导体层和阴极的背面时，形成为P型半导体层的MOS型半导体的沟道区域不被激活。 由此，能够抑制由于晶体管的栅电极引起的控制而发生的漏电流。

公开(公告)号：US5347412A

公开(公告)日：1994-09-13

申请号：US041056

申请日：1993-03-31

Applicant: Hideo Nitta ,  Kunio Kanai ,  Yasuo Arai

Inventor： Hideo Nitta ,  Kunio Kanai ,  Yasuo Arai

IPC: C04B35/00 ,  G11B5/105 ,  G11B5/31 ,  G11B5/60 ,  G11B21/21

CPC classification number: G11B5/105 ,  G11B5/3106

Abstract: A floating magnetic head including a non-magnetic substrate having a two-phase structure which substrate is used as a slider so as to enable a coefficient of thermal expansion to be controlled over a wide range. In air bearing surface is made to be properly rough to improve CSS characteristics of a floating magnetic head. A non-magnetic substrate material contains MnO, NiO, as main components, and Al.sub.2 O.sub.3, as a sub composition, or a part of the sub component is replaced by at least one substance selected from a group consisting of CaO, Y.sub.2 O .sub.3, ZrO .sub.3, ZnO, SrO. The non-magnetic substrate material has a two-phase structure including a rock salt type structure of (MnO, NiO) and a spinel structure of (MnO, NiO) Al.sub.2 O.sub.3 or (MnO, NiO) Al.sub.2 O.sub.3 containing at least one substance selected from a group consisting of CaO, Y.sub.2 O.sub.3, ZrO.sub.3, ZnO, SrO. An average grain size of the substrate is from 5 to 15 .mu.m.

Abstract translation: 包括具有两相结构的非磁性基板的浮动磁头，该基板用作滑块，以便能够在宽范围内控制热膨胀系数。 使空气轴承表面适当粗糙，以改善浮动磁头的CSS特性。 非磁性基板材料含有MnO，NiO作为主要成分，作为副组成的Al 2 O 3或其一部分被选自CaO，Y 2 O 3，ZrO 3中的至少一种物质所代替 ，ZnO，SrO。 非磁性基板材料具有包括（MnO，NiO）的岩盐型结构和（MnO，NiO）Al 2 O 3或（MnO，NiO）Al 2 O 3的尖晶石结构的两相结构，其含有至少一种选自 由CaO，Y2O3，ZrO3，ZnO，SrO组成的组。 基材的平均粒径为5〜15μm。

公开(公告)号：US4793886A

公开(公告)日：1988-12-27

申请号：US69187

申请日：1987-07-02

Applicant: Naomi Okamura ,  Hiroshi Aoki ,  Junzo Makino ,  Hajime Yagi ,  Yasuo Arai ,  Takashi Yamanaka

Inventor： Naomi Okamura ,  Hiroshi Aoki ,  Junzo Makino ,  Hajime Yagi ,  Yasuo Arai ,  Takashi Yamanaka

IPC: C08L35/04 ,  C08L83/04 ,  C09J5/04 ,  C09J5/02

CPC classification number: C09J5/04 ,  C08L35/04 ,  C08L83/04 ,  C09J2483/00 ,  Y10T428/31536

Abstract: A method for bonding two objects by means of the following two adhesives:(A) a moisture-inducible room temperature anion polymerization curing adhesive composed essentially of at least one anion polymerizable compound selected from the group consisting of an .alpha.-cyanoacrylate compound, and a 1,1-disubstituted diene compound;and(B) a room temperature self-curing adhesive containing from 0.05 to 50% by weight of an anion polymerization accelerator, said self-curing adhesive being selected from the group consisting of (1) a room temperature moisture-curing adhesive, (2) a room temperature curing two-part type epoxy resin adhesive, and (3) a room temperature curing synthetic resin aqueous emulsion adhesive, which comprises applying said two adhesives (A) and (B) at the bonding interface of the objects so that they do not contact each other and pressing the objects to each other to bring the two adhesives in contact with each other.

Abstract translation: 一种通过以下两种粘合剂粘结两个物体的方法：（A）一种水分诱导型室温阴离子聚合固化粘合剂，其基本上由至少一种选自由α-氰基丙烯酸酯化合物组成的组的阴离子可聚合化合物和 1,1-二取代二烯化合物; 和（B）含有0.05〜50重量％阴离子聚合促进剂的室温自固化粘合剂，所述自固化粘合剂选自（1）室温湿固化粘合剂，（2） ）室温固化二部分型环氧树脂粘合剂，和（3）室温固化合成树脂水乳液粘合剂，其包括在物体的粘合界面处施加所述两种粘合剂（A）和（B），使得它们 不要彼此接触并且彼此按压物体以使两个粘合剂彼此接触。

公开(公告)号：US20120086079A1

公开(公告)日：2012-04-12

申请号：US13253791

申请日：2011-10-05

Applicant: Hiroki KASAI ,  Yasuo ARAI ,  Takaki HATSUI

Inventor： Hiroki KASAI ,  Yasuo ARAI ,  Takaki HATSUI

IPC: H01L29/772 ,  H01L31/02

CPC classification number: H01L27/14607 ,  H01L27/1203 ,  H01L27/14659

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; an insulation layer on the first semiconductor layer; a second semiconductor layer in the insulation layer; an active element in the second semiconductor layer; a first semiconductor region on the first semiconductor layer and of a second conductivity type; a second semiconductor region in the first semiconductor region and of the second conductivity type with a higher impurity concentration than the first semiconductor region; a first conductor in a through hole in the insulation layer and connected to the second semiconductor region; a second conductor above or within the insulation layer, the second conductor surrounding the first conductor such that an outside edge thereof is outside the second semiconductor region; a third conductor connecting the first and second conductors; and a fourth conductor connected to the first semiconductor layer.

Abstract translation: 半导体器件包括：第一导电类型的第一半导体层; 第一半导体层上的绝缘层; 绝缘层中的第二半导体层; 第二半导体层中的有源元件; 第一半导体区域和第二导电类型的第一半导体区域; 在第一半导体区域中的第二半导体区域和具有比第一半导体区域更高的杂质浓度的第二导电类型的第二半导体区域; 绝缘层中的通孔中的第一导体，并连接到第二半导体区; 绝缘层之上或之内的第二导体，所述第二导体围绕所述第一导体，使得其外边缘在所述第二半导体区域的外部; 连接第一和第二导体的第三导体; 以及连接到第一半导体层的第四导体。