公开(公告)号：US08963246B2

公开(公告)日：2015-02-24

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/144 ,  H01L29/861 ,  H01L29/786

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract translation: 提供了半导体器件和半导体器件的制造方法。 在由高电阻N型衬底形成的N型半导体层内，形成P型阱扩散层和P型提取层，并将其固定为接地电位。 由此，在P型阱扩散层侧扩散的耗尽层未达到P型阱扩散层与埋入氧化膜之间的层间界限。 因此，P型阱扩散层的表面周围的电位保持在接地电位。 因此，当将电压施加到N型半导体层和阴极的背面时，形成为P型半导体层的MOS型半导体的沟道区域不被激活。 由此，能够抑制由于晶体管的栅电极引起的控制而发生的漏电流。

公开(公告)号：US20130043537A1

公开(公告)日：2013-02-21

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

公开(公告)号：US20110204444A1

公开(公告)日：2011-08-25

申请号：US12929820

申请日：2011-02-17

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/78609 ,  H01L29/66772 ,  H01L29/78696

Abstract: A semiconductor integrated device of the invention can enhance a radiation resistance. In an exemplary embodiment, the semiconductor integrated device includes a semiconductor supporting substrate, an insulation layer provided on the semiconductor supporting substrate, and a silicon thin film provided on the insulation layer. A predetermined region in the silicon thin film that is adjacent to the boundary between the insulation layer and the silicon thin film (i.e., boundary neighboring region) has an impurity-concentration-increased region. In this region, the impurity concentration becomes higher as the position approaches the boundary.

Abstract translation: 本发明的半导体集成器件可以提高耐辐射性。 在示例性实施例中，半导体集成器件包括半导体支撑衬底，设置在半导体支撑衬底上的绝缘层和设置在绝缘层上的硅薄膜。 与绝缘层和硅薄膜（即边界相邻区域）之间的边界相邻的硅薄膜中的预定区域具有杂质浓度增加区域。 在该区域中，随着位置接近边界，杂质浓度变高。

公开(公告)号：US07648848B2

公开(公告)日：2010-01-19

申请号：US12073493

申请日：2008-03-06

Applicant: Michihiro Ebe ,  Masao Okihara

Inventor： Michihiro Ebe ,  Masao Okihara

IPC: H01L21/66 ,  H01L21/00 ,  H01L21/84 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L22/20 ,  H01L21/2007 ,  H01L22/12

Abstract: A semiconductor integrated circuit production method prepares an SOI layer thickness database that correlates measurement data of each SOI layer thickness with each SOI substrate identification data. The production method extracts the measurement data for each SOI substrate from the SOI layer thickness database, and carries out layer thickness adjustment surface treatment for the SOI substrates based on these data. A semiconductor integrated circuit production device includes an SOI layer thickness database storage unit for storing the SOI layer thickness database, and a layer thickness adjustment conditions control unit for extracting the measurement data for each SOI substrate from the SOI layer thickness database and deciding conditions for the layer thickness adjustment surface treatment based on these data. The semiconductor integrated circuit production device also includes a surface treatment unit that adjusts SOI layer thickness by carrying out the surface treatment on the SOI layers in accordance with the decided conditions.

Abstract translation: 半导体集成电路制造方法制备将每个SOI层厚度的测量数据与每个SOI衬底识别数据相关联的SOI层厚度数据库。 该制造方法从SOI层厚度数据库中提取每个SOI衬底的测量数据，并且基于这些数据对SOI衬底进行层厚调整表面处理。 半导体集成电路制造装置包括用于存储SOI层厚度数据库的SOI层厚度数据库存储单元和用于从SOI层厚度数据库提取每个SOI衬底的测量数据的层厚调整条件控制单元， 基于这些数据的层厚调整表面处理。 半导体集成电路制造装置还包括：表面处理单元，其通过根据所确定的条件对SOI层进行表面处理来调整SOI层的厚度。

公开(公告)号：US07087967B2

公开(公告)日：2006-08-08

申请号：US10648784

申请日：2003-08-27

Applicant: Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

Inventor： Toru Mori ,  Masao Okihara ,  Shinobu Takehiro

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

Abstract translation: LSI器件包括施加第一驱动电压的芯区域和施加高于上述第一驱动电压的第二驱动电压的接口区域。 LSI器件包括SOI衬底和用于将SOI衬底的SOI层分离成芯区域和界面区域的器件分离区域。 芯区域的SOI层的厚度比界面区域的SOI层的厚度薄。 LSI器件还包括形成在芯区域中的第一MOSFET，其中芯区的SOI层是完全耗尽的Si沟道，并且在界面区域中形成第二MOSFET，并且其中界面区域的SOI层是完全耗尽的 Si通道。

公开(公告)号：US20080237801A1

公开(公告)日：2008-10-02

申请号：US12076053

申请日：2008-03-13

Applicant: Hideki Kisara ,  Masao Okihara

Inventor： Hideki Kisara ,  Masao Okihara

IPC: H01L27/00

CPC classification number: H01L27/13 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/20

Abstract: A semiconductor device includes a resistor element formed in a semiconductor layer of an SOI substrate (Silicon On Insulator). The semiconductor device includes a low concentration impurity area formed in the semiconductor layer as the resistor element; a high concentration impurity area formed in the semiconductor layer as a resistor element wiring portion; and a silicide layer selectively formed on the high concentration impurity area. The high concentration impurity area includes one end portion contacting with an end portion of the low concentration impurity area, and the other end portion contacting with an impurity area of another element.

Abstract translation: 半导体器件包括形成在SOI衬底（绝缘体上硅）的半导体层中的电阻元件。 半导体器件包括在半导体层中形成的低浓度杂质区域作为电阻元件; 形成在半导体层中的高浓度杂质区域作为电阻元件布线部分; 以及选择性地形成在高浓度杂质区上的硅化物层。 高浓度杂质区域包括与低浓度杂质区域的端部接触的一端部，另一端部与另一元件的杂质区域接触。

公开(公告)号：US20080237769A1

公开(公告)日：2008-10-02

申请号：US12048239

申请日：2008-03-14

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L31/0216

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/14632 ,  H01L27/14645

Abstract: A sensor includes a substrate provided with a circuit element forming region and a photodiode forming region, the substrate having a silicon substrate, an insulating layer on the silicon substrate, and a silicon layer on the insulating layer; a photodiode in the silicon layer; a circuit element in the silicon layer; a first interlayer insulating film formed over the silicon layer; a first light-shielding film on the first interlayer film and having an opening in the photodiode forming region; and a first inter-region light-shielding plug arranged between the two regions, for connecting the silicon substrate and the first light-shielding film.

Abstract translation: 传感器包括设置有电路元件形成区域和光电二极管形成区域的基板，所述基板具有硅基板，硅基板上的绝缘层和绝缘层上的硅层; 硅层中的光电二极管; 硅层中的电路元件; 形成在所述硅层上的第一层间绝缘膜; 在所述第一层间膜上具有在所述光电二极管形成区域中具有开口的第一遮光膜; 以及布置在两个区域之间的用于连接硅衬底和第一屏蔽膜的第一区域间屏蔽插头。

公开(公告)号：US20060154431A1

公开(公告)日：2006-07-13

申请号：US11331258

申请日：2006-01-13

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/331

CPC classification number: H01L29/78609 ,  H01L21/76281

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract translation: 绝缘体上硅（SOI）器件的制造工艺包括在501衬底中限定有源区，用给定导电类型的杂质掺杂整个有源区，掩蔽有源区的主要部分，并掺杂 有源区的外围部分至少两次，其中杂质具有相同的导电类型，优选地每次使用不同的掺杂参数。 附加的掺杂在有源区域的外围部分中产生通道停止，抵消在有源区域的外围部分中晶体管阈值电压降低的倾向，从而减轻或消除在晶体管中经常发现的不希望的次阈值突峰 例如，完全耗尽的SOI器件的工作特性。

公开(公告)号：US20050085045A1

公开(公告)日：2005-04-21

申请号：US10687839

申请日：2003-10-20

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/331 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/78609 ,  H01L21/76281

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract translation: 绝缘体上硅（SOI）器件的制造方法包括在SOI衬底中限定有源区，用给定导电类型的杂质掺杂整个有源区，掩蔽有源区的主要部分，并掺杂 有源区的外围部分至少两次，其中杂质具有相同的导电类型，优选地每次使用不同的掺杂参数。 附加掺杂在有源区域的外围部分中产生通道阻挡，抵消在有源区域的外围部分中晶体管阈值电压降低的趋势，从而减轻或消除在晶体管工作中经常发现的不希望的阈值突峰 特征，例如，完全耗尽的SOI器件。

公开(公告)号：US06362474B1

公开(公告)日：2002-03-26

申请号：US09386369

申请日：1999-08-31

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01J37317

CPC classification number: G01N1/32 ,  G01N2033/0095 ,  H01J2237/26

Abstract: Described here is a method of forming a thin-film portion for allowing electrons produced from a transmission electron microscope to pass therethrough at a portion to be observed of a semiconductor and effecting a predetermined etching process on the thin-film portion thereby to create a semiconductor sample for the transmission electron microscope. Prior to the execution of the etching process, grooves for reducing a stress introduced into the thin-film portion by the etching process are defined in the thin-film portion.

Abstract translation: 这里描述的是形成用于使透射电子显微镜产生的电子在半导体观察部分通过的薄膜部分的方法，并对薄膜部分进行预定的蚀刻工艺，从而形成半导体 样品用于透射电子显微镜。 在执行蚀刻工艺之前，在薄膜部分中限定用于通过蚀刻工艺减小引入薄膜部分的应力的沟槽。