发明申请
US20130056865A1 Method of Three Dimensional Integrated Circuit Assembly 有权
三维集成电路组装方法

Method of Three Dimensional Integrated Circuit Assembly
摘要:
A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
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