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公开(公告)号:US09418876B2
公开(公告)日:2016-08-16
申请号:US13224575
申请日:2011-09-02
申请人: Jing-Cheng Lin , Weng-Jin Wu , Shih Ting Lin , Cheng-Lin Huang , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
发明人: Jing-Cheng Lin , Weng-Jin Wu , Shih Ting Lin , Cheng-Lin Huang , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L21/00 , H01L21/56 , H01L21/683 , H01L25/065 , H01L23/00
CPC分类号: H01L21/78 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L24/16 , H01L25/0652 , H01L2221/68327 , H01L2224/16235 , H01L2224/73204 , H01L2224/81005 , H01L2224/81193 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2224/81
摘要: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
摘要翻译: 制造三维集成电路的方法包括将晶片附着到载体上,将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层,将晶片堆叠连接到胶带框架上,并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。
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公开(公告)号:US20130056865A1
公开(公告)日:2013-03-07
申请号:US13224575
申请日:2011-09-02
申请人: Jing-Cheng Lin , Weng-Jin Wu , Shih Ting Lin , Cheng-Lin Huang , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
发明人: Jing-Cheng Lin , Weng-Jin Wu , Shih Ting Lin , Cheng-Lin Huang , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L21/78 , H01L23/498
CPC分类号: H01L21/78 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L24/16 , H01L25/0652 , H01L2221/68327 , H01L2224/16235 , H01L2224/73204 , H01L2224/81005 , H01L2224/81193 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2224/81
摘要: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
摘要翻译: 制造三维集成电路的方法包括将晶片附着到载体上,将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层,将晶片堆叠连接到胶带框架上,并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。
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公开(公告)号:US20130075892A1
公开(公告)日:2013-03-28
申请号:US13246553
申请日:2011-09-27
申请人: Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
发明人: Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
CPC分类号: H01L23/48 , H01L21/6835 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L2221/68327 , H01L2224/0401 , H01L2224/05009 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/3511 , H01L2924/00012 , H01L2224/81 , H01L2924/00 , H01L2224/83
摘要: A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
摘要翻译: 一种用于制造三维集成电路的方法包括:提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠,在第一半导体管芯的第一侧上形成模塑料层,其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出,将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。
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公开(公告)号:US20120045611A1
公开(公告)日:2012-02-23
申请号:US12858211
申请日:2010-08-17
申请人: Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人: Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L23/12 , B32B3/24 , B32B3/26 , B32B38/10 , H01L21/50 , B32B37/02 , B32B37/12 , B32B17/06 , B32B7/12
CPC分类号: G07F17/3213 , B32B17/10 , B32B37/1207 , B32B37/182 , B32B37/185 , B32B2457/14 , H01L21/6835 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
摘要: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.
摘要翻译: 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底,例如玻璃或硅衬底,通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具,用于例如背面处理,例如变薄处理。 在一个实施例中,复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底,使得粘合剂可以延伸到贯穿衬底通孔中。
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公开(公告)号:US08896136B2
公开(公告)日:2014-11-25
申请号:US12827563
申请日:2010-06-30
申请人: Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人: Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L23/544 , H01L29/40 , H01L23/48 , H01L23/52 , H01L21/76 , H01L21/00 , H01L21/4763 , H01L21/44 , H01L21/683
CPC分类号: H01L23/481 , H01L21/30604 , H01L21/6835 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2224/13
摘要: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
摘要翻译: 根据实施例,结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔(TSV); 在所述衬底的所述第二区域上方的隔离层,所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料,所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。
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公开(公告)号:US08846499B2
公开(公告)日:2014-09-30
申请号:US12858211
申请日:2010-08-17
申请人: Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人: Ying-Ching Shih , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L21/30
CPC分类号: G07F17/3213 , B32B17/10 , B32B37/1207 , B32B37/182 , B32B37/185 , B32B2457/14 , H01L21/6835 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
摘要: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.
摘要翻译: 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底,例如玻璃或硅衬底,通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具,用于例如背面处理,例如变薄处理。 在一个实施例中,复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底,使得粘合剂可以延伸到贯穿衬底通孔中。
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公开(公告)号:US20120001337A1
公开(公告)日:2012-01-05
申请号:US12827563
申请日:2010-06-30
申请人: Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人: Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L23/532 , H01L21/71 , H01L23/522
CPC分类号: H01L23/481 , H01L21/30604 , H01L21/6835 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2224/13
摘要: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
摘要翻译: 根据实施例,结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔(TSV); 在所述衬底的所述第二区域上方的隔离层,所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料,所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。
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公开(公告)号:US08581418B2
公开(公告)日:2013-11-12
申请号:US12840949
申请日:2010-07-21
申请人: Weng-Jin Wu , Ying-Ching Shih , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人: Weng-Jin Wu , Ying-Ching Shih , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L23/48
CPC分类号: H01L21/768 , H01L21/56 , H01L21/563 , H01L21/6835 , H01L23/147 , H01L23/293 , H01L23/3107 , H01L23/3128 , H01L23/3157 , H01L23/481 , H01L23/5384 , H01L24/11 , H01L24/14 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/0401 , H01L2224/06181 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/1403 , H01L2224/14181 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/73204 , H01L2224/81005 , H01L2224/81192 , H01L2224/81801 , H01L2224/81895 , H01L2224/83102 , H01L2224/92125 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/81805
摘要: A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first side of the first die through the first metal bump. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion encircling the second die, and an opening exposing the second region of the first side of the first die. A second metal bump of a second horizontal size is formed on the second region of the first side of the first die and extending into the opening of the dielectric layer. The second horizontal size is greater than the first horizontal size. An electrical component is bonded to the first side of the first die through the second metal bump.
摘要翻译: 一种器件包括具有第一侧和与第一侧相对的第二侧的第一管芯,第一侧包括第一区域和第二区域,以及形成在第一侧面的第一区域上的第一水平尺寸的第一金属凸块 的第一个死亡。 通过第一金属凸块将第二模具结合到第一模具的第一侧。 介电层形成在第一管芯的第一侧上,并且包括直接在第二管芯上方的第一部分,环绕第二管芯的第二部分和暴露第一管芯的第一侧的第二区域的开口。 第二水平尺寸的第二金属凸块形成在第一模具的第一侧的第二区域上并且延伸到电介质层的开口中。 第二个水平尺寸大于第一个水平尺寸。 电子部件通过第二金属凸块接合到第一管芯的第一侧。
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公开(公告)号:US20120018876A1
公开(公告)日:2012-01-26
申请号:US12840949
申请日:2010-07-21
申请人: Weng-Jin Wu , Ying-Ching Shih , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人: Weng-Jin Wu , Ying-Ching Shih , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: H01L23/485 , H01L21/768
CPC分类号: H01L21/768 , H01L21/56 , H01L21/563 , H01L21/6835 , H01L23/147 , H01L23/293 , H01L23/3107 , H01L23/3128 , H01L23/3157 , H01L23/481 , H01L23/5384 , H01L24/11 , H01L24/14 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/0401 , H01L2224/06181 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/1403 , H01L2224/14181 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/73204 , H01L2224/81005 , H01L2224/81192 , H01L2224/81801 , H01L2224/81895 , H01L2224/83102 , H01L2224/92125 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/81805
摘要: A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first side of the first die through the first metal bump. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion encircling the second die, and an opening exposing the second region of the first side of the first die. A second metal bump of a second horizontal size is formed on the second region of the first side of the first die and extending into the opening of the dielectric layer. The second horizontal size is greater than the first horizontal size. An electrical component is bonded to the first side of the first die through the second metal bump.
摘要翻译: 一种器件包括具有第一侧和与第一侧相对的第二侧的第一管芯,第一侧包括第一区域和第二区域,以及形成在第一侧面的第一区域上的第一水平尺寸的第一金属凸块 的第一个死亡。 通过第一金属凸块将第二模具结合到第一模具的第一侧。 介电层形成在第一管芯的第一侧上,并且包括直接在第二管芯上方的第一部分,环绕第二管芯的第二部分和暴露第一管芯的第一侧的第二区域的开口。 第二水平尺寸的第二金属凸块形成在第一模具的第一侧的第二区域上并且延伸到电介质层的开口中。 第二个水平尺寸大于第一个水平尺寸。 电子部件通过第二金属凸块接合到第一管芯的第一侧。
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公开(公告)号:US20110309647A1
公开(公告)日:2011-12-22
申请号:US12818022
申请日:2010-06-17
申请人: Ku-Feng Yang , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Chen-Hua Yu
发明人: Ku-Feng Yang , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Chen-Hua Yu
CPC分类号: H01L21/67346 , H01L21/6838 , H01L21/68785
摘要: An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.
摘要翻译: 用于支撑晶片的装置包括基座和气体穿透层。 气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。 气体通道被直接设置在气体穿透层上方的晶片密封。 该装置还包括连接到气体通道的阀。
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