发明申请
US20130083583A1 STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS 有权
具有平行窗口的多芯线绕组组合的最小化

STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS
摘要:
A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements.
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