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1.发明授权公开(公告)号：US08610260B2
公开(公告)日：2013-12-17
申请号：US13439299
申请日：2012-04-04
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , G11C5/04 , G11C5/063 , H01L23/13 , H01L23/3114 , H01L23/3171 , H01L23/48 , H01L23/4824 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/50 , H01L23/52 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L27/108 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/05569 , H01L2224/0557 , H01L2224/06156 , H01L2224/06164 , H01L2224/12105 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/81191 , H01L2224/81193 , H01L2224/81447 , H01L2224/81805 , H01L2224/9202 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06562 , H01L2225/06565 , H01L2225/06589 , H01L2225/1023 , H01L2225/1064 , H01L2225/107 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/3011 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.
摘要翻译： 微电子封装可以包括衬底和微电子元件，其具有面和在其上的一个或多个接触柱，其面对并连接到衬底的表面上的对应接触。 轴向平面可以沿着第一方向的线与面相交，并且相对于元件触点的列居中。 封装端子的列可以沿第一方向延伸。 可以将第二表面的中心区域中的第一端子配置为携带可用于确定微电子元件内的可寻址存储器位置的地址信息。 中心区域可以具有不大于封装端子列之间的最小间距的三倍和五倍的宽度。 轴向平面可以与中心区域相交。
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公开(公告)号：US08525327B2
公开(公告)日：2013-09-03
申请号：US13439286
申请日：2012-04-04
IPC分类号： H01L23/34 , H01L23/498
CPC分类号： H01L23/49838 , G11C5/04 , G11C5/063 , H01L23/13 , H01L23/3114 , H01L23/3171 , H01L23/48 , H01L23/4824 , H01L23/498 , H01L23/49811 , H01L23/49827 , H01L23/50 , H01L23/52 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L27/108 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/05569 , H01L2224/0557 , H01L2224/06156 , H01L2224/06164 , H01L2224/12105 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/81191 , H01L2224/81193 , H01L2224/81447 , H01L2224/81805 , H01L2224/9202 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06562 , H01L2225/06565 , H01L2225/06589 , H01L2225/1023 , H01L2225/1064 , H01L2225/107 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/3011 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.
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3.发明授权Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate 有权使用组合中的重复信号端子的短截线最小化，而无需引线封装衬底公开(公告)号：US08436477B2
公开(公告)日：2013-05-07
申请号：US13439273
申请日：2012-04-04
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , G11C5/063 , H01L23/12 , H01L23/13 , H01L23/49838 , H01L23/50 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/24 , H01L25/0652 , H01L25/0655 , H01L2224/16225 , H01L2224/1715 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2225/06506 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/1023 , H01L2225/107 , H01L2924/01322 , H01L2924/15311 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.
摘要翻译： 微电子封装可以包括其上具有面和多个元件触点的微电子元件，具有第一和第二表面的衬底以及被配置为将封装与外部元件连接的第二表面上的端子。 微电子元件可以包括多个堆叠的电互连半导体芯片。 衬底可以具有面向微电子元件的元件触点并且与其接合的触点。 端子可以包括布置在第一和第二平行栅格内的位置处的第一端子。 每个电网的第一个端子可被配置为承载可由微电子封装内的电路使用的地址信息，以从微电子元件内的所有可寻址的存储单元中确定可寻址的存储器位置。 第一网格中的第一终端的信号分配可以是第二网格中的第一终端的信号分配的镜像。
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4.发明申请公开(公告)号：US20130083583A1
公开(公告)日：2013-04-04
申请号：US13440515
申请日：2012-04-05
IPC分类号： G11C5/06
CPC分类号： H01L25/105 , H01L23/13 , H01L23/3128 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/06156 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01087 , H01L2924/01322 , H01L2924/09701 , H01L2924/1434 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements.
摘要翻译： 微电子封装可以包括具有第一和第二相对表面的衬底以及在第一和第二表面之间延伸的第一和第二孔，第一和第二微电子元件各自具有面向衬底的第一表面的表面， 并且在每个微电子元件的触点和端子之间电连接引线。 孔可以具有在相应孔的长度方向上延伸的第一和第二平行轴线。 第二表面的中心区域可以设置在第一和第二轴线之间。 终端可以被配置为承载可由微电子封装内的电路使用的地址信息，以从微电子元件内的存储器存储阵列的所有可寻址的存储器位置中确定可寻址的存储器位置。
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5.发明申请STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE 失效使用信号终端在信号终端中使用双绞线组合的最小化，而不需要将线束封装在基板上公开(公告)号：US20130082374A1
公开(公告)日：2013-04-04
申请号：US13439228
申请日：2012-04-04
IPC分类号： H01L23/498
CPC分类号： H01L25/0657 , G11C5/063 , H01L23/12 , H01L23/13 , H01L23/49838 , H01L23/50 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/24 , H01L25/0652 , H01L25/0655 , H01L2224/16225 , H01L2224/1715 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2225/06506 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/1023 , H01L2225/107 , H01L2924/01322 , H01L2924/15311 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.
摘要翻译： 微电子组件可以包括在其相应的第一和第二表面处具有第一和第二面板触点的电路板，以及每个具有安装到各个面板触点的端子的第一和第二微电子封装。 每个封装可以包括具有面和其上的触点的微电子元件，具有第一和第二表面的基板，以及在第二表面上的端子，用于将封装与外部元件连接。 端子可以包括在第一和第二平行网格内的位置处的第一端子。 第一终端可以被配置为承载可用于封装内的电路的地址信息，以从微电子元件内的存储器存储阵列的所有可寻址的存储器单元中确定可寻址的存储器位置。 第一网格中的第一终端的信号分配可以是第二网格中的第一终端的信号分配的镜像。
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6.发明授权Stub minimization for multi-die wirebond assemblies with orthogonal windows 有权具有正交窗口的多芯片接线组件的短截线最小化公开(公告)号：US08278764B1
公开(公告)日：2012-10-02
申请号：US13354772
申请日：2012-01-20
CPC分类号： H01L25/105 , H01L23/13 , H01L23/3128 , H01L25/0652 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/107 , H01L2924/01087 , H01L2924/01322 , H01L2924/09701 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic package can include a substrate having first, second, and third apertures extending between first and second surfaces thereof, first, second, and third microelectronic elements each having a surface facing the first surface, and a plurality of terminals exposed at a central region of the second surface. The apertures can have first, second, and third axes extending in directions of the lengths of the respective apertures. The first and second axes can be parallel to one another. The third axis can be transverse to the first axis. The central region of the second surface of the substrate can be disposed between the first and second axes. The terminals can be configured to carry sufficient address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the microelectronic elements.
摘要翻译： 微电子封装可以包括具有在其第一和第二表面之间延伸的第一，第二和第三孔的衬底，每个具有面向第一表面的表面的第一，第二和第三微电子元件，以及暴露在中心区域处的多个端子 的第二个表面。 孔可以具有在相应孔的长度方向上延伸的第一，第二和第三轴。 第一和第二轴线可以彼此平行。 第三轴线可以横向于第一轴线。 基板的第二表面的中心区域可以设置在第一和第二轴线之间。 终端可被配置为承载可用于封装内的电路的足够的地址信息，以从至少一个微电子元件内的存储器存储阵列的所有可寻址的存储单元中确定可寻址的存储器位置。
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7.发明授权Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate 失效使用组合中的重复信号端子的短截线最小化，而无需引线封装衬底公开(公告)号：US08659139B2
公开(公告)日：2014-02-25
申请号：US13439228
申请日：2012-04-04
CPC分类号： H01L25/0657 , G11C5/063 , H01L23/12 , H01L23/13 , H01L23/49838 , H01L23/50 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/24 , H01L25/0652 , H01L25/0655 , H01L2224/16225 , H01L2224/1715 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2225/06506 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/1023 , H01L2225/107 , H01L2924/01322 , H01L2924/15311 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.
摘要翻译： 微电子组件可以包括在其相应的第一和第二表面处具有第一和第二面板触点的电路板，以及每个具有安装到各个面板触点的端子的第一和第二微电子封装。 每个封装可以包括具有面和其上的触点的微电子元件，具有第一和第二表面的基板，以及在第二表面上的端子，用于将封装与外部元件连接。 端子可以包括在第一和第二平行网格内的位置处的第一端子。 第一终端可以被配置为承载可用于封装内的电路的地址信息，以从微电子元件内的存储器存储阵列的所有可寻址的存储器单元中确定可寻址的存储器位置。 第一网格中的第一终端的信号分配可以是第二网格中的第一终端的信号分配的镜像。
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8.发明授权公开(公告)号：US08436457B2
公开(公告)日：2013-05-07
申请号：US13337565
申请日：2011-12-27
IPC分类号： H01L21/02
CPC分类号： H01L25/105 , H01L23/13 , H01L23/3128 , H01L25/0652 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/107 , H01L2924/01087 , H01L2924/01322 , H01L2924/09701 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.
摘要翻译： 微电子封装可以包括具有第一和第二相对表面的衬底以及在第一和第二表面之间延伸的第一和第二孔，第一和第二微电子元件各自具有面向衬底的第一表面的表面， 并且在每个微电子元件的触点和端子之间电连接引线。 孔可以具有在相应孔的长度方向上延伸的第一和第二平行轴线。 第二表面可以具有设置在第一和第二轴之间的中心区域。 每个微电子元件可以体现更多数量的有源器件以提供比任何其他功能的存储器阵列功能。 这些端子可以被配置为承载传送到微电子封装的所有地址信号。
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9.发明申请STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS 有权使用不带WINDOWS的WIREBOND组件的终端设备的最小化公开(公告)号：US20130082381A1
公开(公告)日：2013-04-04
申请号：US13440212
申请日：2012-04-05
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , G11C5/04 , G11C5/063 , G11C5/066 , G11C8/18 , H01L23/02 , H01L23/13 , H01L23/48 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0655 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/49113 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2225/107 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/85
摘要： A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.
摘要翻译： 具有存储器阵列的微电子元件具有背向微电子封装的衬底的前表面，并且通过在前表面上方延伸的导电结构与衬底电连接。 第一端子设置在封装的第一和第二平行格栅内的位置。 每个网格的第一终端被配置为承载可用于从存储器存储阵列的所有可用可寻址存储器位置中确定可寻址存储器位置的地址信息。 第一网格中的第一终端具有作为第二网格中的第一终端的信号分配的镜像的信号分配。
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公开(公告)号：US08405207B1
公开(公告)日：2013-03-26
申请号：US13440313
申请日：2012-04-05
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , G06F1/18 , H01L21/563 , H01L23/3128 , H01L23/36 , H01L23/3672 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L23/525 , H01L23/5385 , H01L24/24 , H01L24/73 , H01L25/0655 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06551 , H01L2225/06562 , H01L2225/06589 , H01L2924/00 , H01L2924/00012 , H01L2924/01322 , H01L2924/15311 , H01L2924/18161 , H01L2924/3011 , H05K1/0243 , H05K1/181 , H05K2201/10159 , H05K2201/10545 , H05K2201/10734 , Y02P70/611
摘要： A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region.
摘要翻译： 微电子封装可以包括衬底和微电子元件，微电子元件具有面向衬底的第一表面的后表面，正面和沿第一方向延伸的元件触点列。 微电子元件的边缘可以限定在垂直于后表面的第一方向和第三方向上延伸的轴向平面。 封装可以包括在基板的第二表面处沿第一方向延伸的端子列。 终端可以包括暴露在第二表面的中心区域中的第一终端，并且被配置为承载可用于封装内的电路的地址信息，以确定微电子元件内的可寻址存储器位置。 中心区域可以具有不超过端子的任何两个相邻列之间的最小间距的三倍和五倍的宽度。 轴向平面可以与中心区域相交。
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