发明申请
US20130127046A1 REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY 有权
三维半导体器件接合和​​组装过程中降低静电放电的可能性

REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY
摘要:
Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.
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