发明申请
US20130127046A1 REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY
有权
三维半导体器件接合和组装过程中降低静电放电的可能性
- 专利标题: REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY
- 专利标题(中): 三维半导体器件接合和组装过程中降低静电放电的可能性
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申请号: US13470692申请日: 2012-05-14
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公开(公告)号: US20130127046A1公开(公告)日: 2013-05-23
- 发明人: Brian M. Henderson , Ronnie A. Lindley , Dong Wook Kim , Reza Jalilizeinali , Shiqun Gu , Matthiew M. Nowak
- 申请人: Brian M. Henderson , Ronnie A. Lindley , Dong Wook Kim , Reza Jalilizeinali , Shiqun Gu , Matthiew M. Nowak
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM INCORPORATED
- 当前专利权人: QUALCOMM INCORPORATED
- 当前专利权人地址: US CA San Diego
- 主分类号: H01L23/488
- IPC分类号: H01L23/488 ; H01L21/50
摘要:
Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.
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