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13 条记录 (耗时 0.028 秒)

    Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly
    3.
    发明申请
    Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly 有权
    降低3D半导体器件粘合和组装过程中静电放电的敏感性

    公开(公告)号：US20100258949A1

    公开(公告)日：2010-10-14

    申请号：US12421096

    申请日：2009-04-09

    申请人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    发明人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    IPC分类号： H01L23/52 ,  H01L21/50 ,  H05K3/36 ,  H05K13/00

    CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L21/67092 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513

    摘要： A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

    摘要翻译： 一种组装堆叠IC器件时降低静电放电敏感性的方法。 该方法包括将第一半导体器件的接地平面和第二半导体器件的接地平面耦合到基本上相同的电位。 第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。 电耦合第一和第二半导体器件的接地平面产生优选的接地静电放电路径，从而最小化对敏感电路元件的潜在损害。

    Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly
    4.
    发明授权
    Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly 有权
    在3D半导体器件接合和​​组装期间降低对静电放电的敏感性

    公开(公告)号：US08198736B2

    公开(公告)日：2012-06-12

    申请号：US12421096

    申请日：2009-04-09

    申请人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    发明人： Brian M. Henderson ,  Reza Jalilizeinali ,  Shiqun Gu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L21/67092 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513

    摘要： A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

    摘要翻译： 一种组装堆叠IC器件时降低静电放电敏感性的方法。 该方法包括将第一半导体器件的接地平面和第二半导体器件的接地平面耦合到基本上相同的电位。 第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。 电耦合第一和第二半导体器件的接地平面产生优选的接地静电放电路径，从而最小化对敏感电路元件的潜在损害。

    Integrated circuit for measuring mask misalignment
    9.
    发明授权
    Integrated circuit for measuring mask misalignment 失效
    用于测量掩模未对准的集成电路

    公开(公告)号：US4647850A

    公开(公告)日：1987-03-03

    申请号：US658416

    申请日：1984-10-05

    申请人： Brian M. Henderson ,  Alan M. Gundlach ,  Anthony J. Walton

    发明人： Brian M. Henderson ,  Alan M. Gundlach ,  Anthony J. Walton

    IPC分类号： G01B7/00 ,  G01B7/31 ,  G01R27/14 ,  H01L21/66

    CPC分类号： G01B7/31 ,  G01B7/003 ,  Y10S148/102

    摘要： An integrated circuit for measuring conductor misalignment comprises: a set of 2n+1 conductor pairs where n is a predetermined positive integer; each conductor pair includes a U-shaped conductor having a central axis; each conductor pair also includes a rectangular shaped conductor having a central axis and which is narrow enough to fit between the legs of the U-shaped conductor provided their central axis are aligned; and the rectangular shaped conductor of each conductor pair has its central axis a distance .delta.+k.DELTA.d from the central axis of the U-shaped conductor where .DELTA.d is a fixed increment, k is an integer between +n and -n that differs for each conductor pair, and .delta.is a misalignment between the central axis of each conductor pair.

    摘要翻译： 用于测量导体未对准的集成电路包括：一组2n + 1个导体对，其中n是预定的正整数; 每个导体对包括具有中心轴线的U形导体; 每个导体对还包括具有中心轴线的矩形导体，并且其矩形足够窄以适合于U形导体的腿之间，只要它们的中心轴线对齐; 并且每个导体对的矩形导体的中心轴距离U形导体的中心轴的距离δ+ k DELTA d，其中DELTA d是固定的增量，k是在+ n之间的整数，并且-n不同 对于每个导体对，delta是每个导体对的中心轴之间的未对准。