A method of generating a hardware design for a stream processor. The method includes defining a graph representing a processing operation designating processes to be implemented in hardware as part of the stream processor. The graph represents the processing operation in the time domain as a function of clock cycles and includes at least one data path. At least one stream offset object is provided located at a particular point in the data path. The stream offset object is operable to access, for a particular clock cycle and for the particular point in the data path, data values from a clock cycle different from the particular clock cycle