公开(公告)号：US09584594B2

公开(公告)日：2017-02-28

申请号：US14251360

申请日：2014-04-11

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Oliver Pell ,  Peter Sanders ,  Nicolas Norvez

IPC: G06F15/173 ,  H04L29/08 ,  G06F9/50

CPC classification number: H04L67/1006 ,  G06F9/4806 ,  G06F9/5005 ,  G06F9/5044 ,  G06F9/5077 ,  G06F2209/5022 ,  H04L67/1025 ,  H04L67/1036

Abstract: A system and method of dynamically provisioning virtualized computational resources in a networked computer architecture includes at least one client device operable to run one or more client applications, at least one server device and a resource controller. Each server device comprises one or more physical processors with local memory. Each server device provides a virtual resource layer through which one or more virtual processing resources can be defined and through which the physical processors of the server device can be assigned to the virtual processing resources. In use, one or more virtual processing resources is assigned to a client application for processing of data processing workloads. The resource controller then monitors the utilization of each virtual processing resource and/or any physical processor assigned to the virtual processing resource. The resource controller can dynamically adjust which, and how many, physical processors are assigned to the virtual processing resource.

Abstract translation: 在联网的计算机体系结构中动态地配置虚拟计算资源的系统和方法包括至少一个可操作以运行一个或多个客户端应用，至少一个服务器设备和资源控制器的客户端设备。 每个服务器设备包括具有本地存储器的一个或多个物理处理器。 每个服务器设备提供虚拟资源层，通过该虚拟资源层可以定义一个或多个虚拟处理资源，通过该虚拟资源层可以将服务器设备的物理处理器分配给虚拟处理资源。 在使用中，将一个或多个虚拟处理资源分配给用于处理数据处理工作负载的客户端应用程序。 资源控制器然后监视分配给虚拟处理资源的每个虚拟处理资源和/或任何物理处理器的利用率。 资源控制器可以动态地调整分配给虚拟处理资源的物理处理器和数量。

公开(公告)号：US10715587B2

公开(公告)日：2020-07-14

申请号：US14251379

申请日：2014-04-11

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Oliver Pell

IPC: H04L29/08 ,  G06F9/50 ,  H04L12/911

Abstract: A networked computational architecture for provisioning of virtualized computational resources. The architecture is accessible by a client application run on a client device. The architecture includes a hardware layer having a plurality of server devices, each server device having at least one physical processor having a local memory. A resource controller is provided and operable to allocate a plurality of server devices to a client application for data processing and to assign control information to the client application. The control information specifies the required allocation of a data processing workload to each server device allocated to the client application. The architecture is configured such that client applications send the data processing workload directly to each server in accordance with the control information. Thus, a networked architecture is load balanced indirectly without requiring a load balancer to be located in the data path between the client and the server.

公开(公告)号：US08739101B1

公开(公告)日：2014-05-27

申请号：US13683743

申请日：2012-11-21

Applicant: Maxeler Technologies Ltd.

Inventor： Robert Gwilym Dimond

IPC: G06F17/50 ,  G06F9/44 ,  G06F7/38 ,  G06F7/32 ,  G06F9/445 ,  G06F9/455 ,  G06F9/38

CPC classification number: G06F17/5054 ,  G06F7/32 ,  G06F7/38 ,  G06F9/382 ,  G06F9/4403 ,  G06F9/445 ,  G06F9/44505 ,  G06F9/455 ,  G06F17/505 ,  G06F17/5077

Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.

Abstract translation: 配置流水线并行流处理器的硬件设计的方法包括获取表示时域中的处理操作的调度图，作为时钟周期的函数。 该图包括要在硬件中实现的数据路径，作为流处理器的一部分，输入，输出和并行分支，以使数据值能够作为增加时钟周期的函数从输入流输出到输出。 数据路径被划分成多个离散区域，每个区域在不同的时钟相位上操作并具有离散的控制逻辑元件。 用于对齐由具有不同时钟相位的区域之间的边界分隔的数据的相移寄存器被引入边界的数据路径。 图形和控制逻辑元素定义流水线并行流处理器的硬件设计。

公开(公告)号：US09501325B2

公开(公告)日：2016-11-22

申请号：US14251391

申请日：2014-04-11

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Oliver Pell ,  Peter Sanders ,  James Barry Spooner

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  H04L12/911

CPC classification number: G06F9/5044 ,  G06F9/3877 ,  G06F9/455 ,  G06F9/5027 ,  G06F9/5077 ,  G06F2009/45595 ,  H04L47/821

Abstract: A system and method of provisioning virtualized computational resources in a networked computer architecture includes a client device to run a client application, a server device, and a resource controller. The server device includes one or more processors having a local memory, and provides a virtual resource layer through which one or more virtual processing resources can be defined and through which one or more physical processors of said server device can be assigned to one or more of said virtual processing resources. The physical processors process at least a part of a data processing workload from said one or more client applications, each workload including input data having a static data part and a dynamic data part. The resource controller assigns a virtual processing resource to a plurality of client applications, where the input data for the workload of each client application has the same static data part.

Abstract translation: 在联网计算机体系结构中提供虚拟化计算资源的系统和方法包括运行客户端应用的客户端设备，服务器设备和资源控制器。 服务器设备包括具有本地存储器的一个或多个处理器，并且提供虚拟资源层，通过该虚拟资源层可以定义一个或多个虚拟处理资源，并且通过该虚拟资源层可以将所述服务器设备的一个或多个物理处理器分配给一个或多个 说虚拟处理资源。 物理处理器处理来自所述一个或多个客户端应用的数据处理工作负载的至少一部分，每个工作负载包括具有静态数据部分和动态数据部分的输入数据。 资源控制器将虚拟处理资源分配给多个客户端应用，其中每个客户端应用的工作负荷的输入数据具有相同的静态数据部分。

公开(公告)号：US20150296002A1

公开(公告)日：2015-10-15

申请号：US14251379

申请日：2014-04-11

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Oliver Pell

IPC: H04L29/08 ,  H04L12/911

Abstract: A networked computational architecture for provisioning of virtualized computational resources. The architecture is accessible by a client application run on a client device. The architecture includes a hardware layer having a plurality of server devices, each server device having at least one physical processor having a local memory. A resource controller is provided and operable to allocate a plurality of server devices to a client application for data processing and to assign control information to the client application. The control information specifies the required allocation of a data processing workload to each server device allocated to the client application. The architecture is configured such that client applications send the data processing workload directly to each server in accordance with the control information. Thus, a networked architecture is load balanced indirectly without requiring a load balancer to be located in the data path between the client and the server.

Abstract translation: 用于提供虚拟化计算资源的联网计算架构。 该架构可以由客户端设备上运行的客户端应用程序访问。 该架构包括具有多个服务器设备的硬件层，每个服务器设备具有至少一个具有本地存储器的物理处理器。 提供资源控制器并且可操作以将多个服务器设备分配给用于数据处理的客户端应用，并且向客户端应用分配控制信息。 控制信息指定将数据处理工作负载分配给分配给客户端应用程序的每个服务器设备所需的分配。 该架构被配置为使得客户端应用程序根据控制信息将数据处理工作负载直接发送到每个服务器。 因此，网络架构间接负载均衡，而不需要将负载均衡器放置在客户端和服务器之间的数据路径中。

公开(公告)号：US08847798B2

公开(公告)日：2014-09-30

申请号：US13717188

申请日：2012-12-17

Applicant: Maxeler Technologies Ltd.

Inventor： Oliver Pell ,  Stephen Girdlestone ,  Henning Meyer

IPC: H03M7/30 ,  H03M5/14

CPC classification number: H03M5/145 ,  H03M7/30 ,  H03M7/46 ,  H03M7/6023 ,  H03M7/6029

Abstract: A method of data compression includes obtaining a data set comprising a sequence of data blocks comprising a predetermined number of data items, partitioning said data set into one or more groups each comprising a predetermined number of data blocks, and performing data compression on one or more groups of data blocks. Data compression is performed by associating a control data item with each of said blocks, generating a control vector comprising the control data items assigned to each of said blocks within a group, removing data blocks comprising entirely data items having said specified value, compressing data blocks comprising at least one data item having a value different from said specified value using a fixed-rate compression scheme, providing a compressed data stream comprising said compressed data blocks, and providing an associated control vector stream to enable control of said compressed data stream.

Abstract translation: 一种数据压缩方法包括获得包括包括预定数量的数据项的数据块序列的数据集，将所述数据集划分为一个或多个组，每个组包括预定数量的数据块，并且对一个或多个数据进行数据压缩 数据块组。 通过将控制数据项与每个所述块相关联来执行数据压缩，产生包括分配给组内的每个所述块的控制数据项的控制向量，去除包含完全具有所述指定值的数据项的数据块，压缩数据块 包括使用固定速率压缩方案具有不同于所述指定值的值的至少一个数据项，提供包括所述压缩数据块的压缩数据流，以及提供关联的控制向量流以使得能够控制所述压缩数据流。

公开(公告)号：US08701069B1

公开(公告)日：2014-04-15

申请号：US13683769

申请日：2012-11-21

Applicant: Maxeler Technologies Ltd.

Inventor： Robert Gwilym Dimond

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/08

Abstract: A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, functional objects, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The functional objects are grouped based upon having a cycle position dependent upon common factors. Common control logic elements are allocated to groups of functional objects. The graph and allocated control logic is used to define a hardware design for the pipelined parallel stream processor.

Abstract translation: 利用高级合成来自动配置用于流水线并行流处理器的硬件设计的控制逻辑的方法包括获取表示时域中的处理操作的调度图，作为时钟周期的函数。 该图包括要作为流处理器的一部分在硬件中实现的数据路径，输入，输出，功能对象和并行分支，以使数据值能够从输入到输出中的数据流作为增加时钟的函数 周期。 基于具有取决于共同因素的循环位置，功能对象被分组。 公共控制逻辑元件分配给功能对象组。 图形和分配的控制逻辑用于定义流水线并行流处理器的硬件设计。

公开(公告)号：US20150295853A1

公开(公告)日：2015-10-15

申请号：US14251391

申请日：2014-04-11

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Oliver PELL ,  Peter SANDERS ,  James Barry SPOONER

IPC: H04L12/911 ,  G06F9/455

CPC classification number: G06F9/5044 ,  G06F9/3877 ,  G06F9/455 ,  G06F9/5027 ,  G06F9/5077 ,  G06F2009/45595 ,  H04L47/821

Abstract: A system and method of provisioning virtualized computational resources in a networked computer architecture includes a client device to run a client application, a server device, and a resource controller. The server device includes one or more processors having a local memory, and provides a virtual resource layer through which one or more virtual processing resources can be defined and through which one or more physical processors of said server device can be assigned to one or more of said virtual processing resources. The physical processors process at least a part of a data processing workload from said one or more client applications, each workload including input data having a static data part and a dynamic data part. The resource controller assigns a virtual processing resource to a plurality of client applications, where the input data for the workload of each client application has the same static data part.

Abstract translation: 在联网计算机体系结构中提供虚拟化计算资源的系统和方法包括运行客户端应用的客户端设备，服务器设备和资源控制器。 服务器设备包括具有本地存储器的一个或多个处理器，并且提供虚拟资源层，通过该虚拟资源层可以定义一个或多个虚拟处理资源，并且通过该虚拟资源层可以将所述服务器设备的一个或多个物理处理器分配给一个或多个 说虚拟处理资源。 物理处理器处理来自所述一个或多个客户端应用的数据处理工作负载的至少一部分，每个工作负载包括具有静态数据部分和动态数据部分的输入数据。 资源控制器将虚拟处理资源分配给多个客户端应用，其中每个客户端应用的工作负荷的输入数据具有相同的静态数据部分。

公开(公告)号：US08930876B2

公开(公告)日：2015-01-06

申请号：US13725345

申请日：2012-12-21

Applicant: Maxeler Technologies, Ltd.

Inventor： Oliver Pell ,  Itay Greenspon ,  James Barry Spooner ,  Robert Gwilym Dimond

IPC: G06F17/50 ,  G06F11/22 ,  G06F11/30 ,  G06F13/36 ,  G06F11/36 ,  G06F15/76

CPC classification number: G06F15/76 ,  G06F11/3024 ,  G06F11/3027 ,  G06F11/3093 ,  G06F11/3636 ,  G06F13/36

Abstract: Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.

Abstract translation: 公开了一种监视流处理器的可编程逻辑的操作的方法，所述方法包括：生成表示要在硬件中实现的可编程逻辑的图，所述图包括连接图中节点的节点和边; 在每个边缘插入监视硬件以监视沿着边缘的数据流。 还公开了监视用于流处理器的可编程逻辑的操作的方法，所述方法包括：生成表示要在硬件中实现的可编程逻辑的图，所述图包括连接图中的节点的节点和边; 在至少一个边缘上插入被配置为从上游节点接收数据的数据生成硬件，并以与所接收的数据相同的流控制模式的已知值生成数据，以便向连接的节点向前传输。

公开(公告)号：US20140143744A1

公开(公告)日：2014-05-22

申请号：US13683743

申请日：2012-11-21

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Robert Gwilym DIMOND

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F7/32 ,  G06F7/38 ,  G06F9/382 ,  G06F9/4403 ,  G06F9/445 ,  G06F9/44505 ,  G06F9/455 ,  G06F17/505 ,  G06F17/5077

Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.

Abstract translation: 配置流水线并行流处理器的硬件设计的方法包括获取表示时域中的处理操作的调度图，作为时钟周期的函数。 该图包括要在硬件中实现的数据路径，作为流处理器的一部分，输入，输出和并行分支，以使数据值能够作为增加时钟周期的函数从输入流输出到输出。 数据路径被划分成多个离散区域，每个区域在不同的时钟相位上操作并具有离散的控制逻辑元件。 用于对齐由具有不同时钟相位的区域之间的边界分隔的数据的相移寄存器被引入边界的数据路径。 图形和控制逻辑元素定义流水线并行流处理器的硬件设计。