Invention Application
- Patent Title: Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit
- Patent Title (中): 静态随机存取存储器在大规模集成电路不同位置的电气屏蔽
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Application No.: US13723639Application Date: 2012-12-21
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Publication No.: US20130176772A1Publication Date: 2013-07-11
- Inventor: Xiaowei Deng , Yang Yi , Wah Kit Loh
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Main IPC: G11C29/50
- IPC: G11C29/50

Abstract:
A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.
Public/Granted literature
- US09208832B2 Functional screening of static random access memories using an array bias voltage Public/Granted day:2015-12-08
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