Invention Application
US20130176772A1 Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit 有权
静态随机存取存储器在大规模集成电路不同位置的电气屏蔽

Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit
Abstract:
A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.
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