公开(公告)号：US09208832B2

公开(公告)日：2015-12-08

申请号：US13723639

申请日：2012-12-21

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Yang Yi ,  Wah Kit Loh

IPC: G11C5/14 ,  G11C29/50 ,  G11C29/02 ,  G11C29/12 ,  G11C29/26 ,  G11C11/41 ,  G11C29/40 ,  G11C29/04

CPC classification number: G11C5/147 ,  G11C11/41 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/40 ,  G11C29/50004 ,  G11C2029/0401

Abstract: A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

Abstract translation: 一种测试包括多个存储器阵列实例的大规模集成电路的方法，以及用于辅助这种测试的集成电路结构。 在一个实施例中，通过提取布局参数和随后的电路模拟来确定阵列偏置导体中的寄生电阻引起的电压降，其导出每个存储器阵列操作期间那些导体中的电压降。 在另一个实施例中，来自每个存储器阵列的感测线选择性地连接到集成电路的测试感测端子，在该测试检测端子处外部测量每个存储器阵列处的阵列偏置电压。 可以进行施加电压的反馈控制以达到期望的阵列偏置电压。

公开(公告)号：US20130176772A1

公开(公告)日：2013-07-11

申请号：US13723639

申请日：2012-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Yang Yi ,  Wah Kit Loh

IPC: G11C29/50

CPC classification number: G11C5/147 ,  G11C11/41 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/40 ,  G11C29/50004 ,  G11C2029/0401

Abstract: A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

Abstract translation: 公开了一种测试包括多个存储器阵列实例的大规模集成电路的方法以及用于辅助这种测试的集成电路结构。 在一个实施例中，通过提取布局参数和随后的电路模拟来确定阵列偏置导体中的寄生电阻引起的电压降，其导出每个存储器阵列操作期间那些导体中的电压降。 在另一个实施例中，来自每个存储器阵列的感测线选择性地连接到集成电路的测试感测端子，在该测试检测端子处外部测量每个存储器阵列处的阵列偏置电压。 可以进行施加电压的反馈控制以达到期望的阵列偏置电压。