A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period.