公开(公告)号：US20190250197A1

公开(公告)日：2019-08-15

申请号：US16247036

申请日：2019-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroto SUZUKI

IPC: G01R27/26 ,  H03F3/45

CPC classification number: G01R27/26 ,  H03F3/45071 ,  H03F2200/129 ,  H03F2200/156 ,  H03F2200/228 ,  H03F2200/231 ,  H03F2203/45514 ,  H03F2203/45526 ,  H03F2203/45528 ,  H03F2203/45534

Abstract: A provided impedance measuring semiconductor circuit can suppress the influence of sensors on the measurements of other sensors in the measurements of the sensors. According to an embodiment, an impedance measuring semiconductor circuit includes a first resistance element, an operational amplifier having a positive input terminal and an output terminal, the positive input terminal receiving a predetermined set voltage, the output terminal being coupled to one end of the first resistance element, a first output-side switch that electrically couples or decouples a first sensor and the other end of the first resistance element, a second output-side switch that electrically couples or decouples a second sensor and the other end of the first resistance element, a first input-side switch that electrically couples or decouples the first sensor and a negative input terminal, and a second input-side switch that electrically couples or decouples the second sensor and the negative input terminal.

公开(公告)号：US20130265180A1

公开(公告)日：2013-10-10

申请号：US13794308

申请日：2013-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi MATSUMOTO ,  Masao ITO ,  Osamu MATSUMOTO ,  Hiroto SUZUKI

IPC: H03M1/46 ,  H03M1/38

CPC classification number: H03M1/38 ,  H03M1/0697 ,  H03M1/46

Abstract: A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period.

Abstract translation: 在逐次逼近寄存器A / D转换器的操作基于集成电路中的电路定时受到影响的定时，获得N位输出的逐次逼近寄存器A / D转换器中断操作。 A / D转换器将采样信号和比较参考电压进行比较，其中采样模拟信号的采样周期，将采样信号顺序地与每个位的比较电压相比较的N个状态的比较周期 ，以及比较期间M州的储备期。 当操作暂时中断时，A / D转换器执行位的比较操作，而在保留期间不进行比较。