Invention Application
US20140091374A1 STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS
有权
用于集成CMOS和Si纳米光子的应力工程多层
- Patent Title: STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS
- Patent Title (中): 用于集成CMOS和Si纳米光子的应力工程多层
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Application No.: US13629910Application Date: 2012-09-28
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Publication No.: US20140091374A1Publication Date: 2014-04-03
- Inventor: Solomon Assefa , Tymon Barwicz , Swetha Kamlapurkar , Marwan H. Khater , Steven M. Shank , Yurii A. Vlasov
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Main IPC: H01L27/14
- IPC: H01L27/14 ; H01L31/18
Abstract:
A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.
Public/Granted literature
- US08765536B2 Stress engineered multi-layers for integration of CMOS and Si nanophotonics Public/Granted day:2014-07-01
Information query
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