发明申请
- 专利标题: LAMINATION LAYER TYPE SEMICONDUCTOR PACKAGE
- 专利标题(中): 层压层型半导体封装
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申请号: US14089724申请日: 2013-11-25
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公开(公告)号: US20140145323A1公开(公告)日: 2014-05-29
- 发明人: Kyung Ho LEE , Hyun Bok KWON , Seung Wan WOO , Young Nam HWANG , Suk Jin HAM , Po Chul KIM , So Hyang EUN , Se Jun PARK
- 申请人: Samsung Electro-Mechanics Co., Ltd.
- 申请人地址: KR Suwon-si
- 专利权人: SAMSUNG ELECTRO-MECHANICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRO-MECHANICS CO., LTD.
- 当前专利权人地址: KR Suwon-si
- 优先权: KR10-2012-0134493 20121126
- 主分类号: H01L23/373
- IPC分类号: H01L23/373
摘要:
Disclosed herein is a lamination layer type semiconductor package, and more particularly, a lamination layer type semiconductor package capable of maintaining a thickness of a package on package structure at a minimum and minimizing a warpage defect by mounting two chips so as to correspond to each other. The lamination layer type semiconductor package includes: an upper package having an upper flip chip mounted on an upper substrate; a lower package having a lower flip chip mounted on a lower substrate and disposed so as to closely adhere the upper flip chip and the lower flip chip to each other; a heat dissipation adhesive member adhesively fixing the upper flip chip and the lower flip chip and dissipating heat generated from the upper flip chip and the lower flip chip; and a molding member molding between the upper substrate and the lower substrate.
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