LAMINATION LAYER TYPE SEMICONDUCTOR PACKAGE
    1.
    发明申请
    LAMINATION LAYER TYPE SEMICONDUCTOR PACKAGE 审中-公开
    层压层型半导体封装

    公开(公告)号:US20140145323A1

    公开(公告)日:2014-05-29

    申请号:US14089724

    申请日:2013-11-25

    IPC分类号: H01L23/373

    摘要: Disclosed herein is a lamination layer type semiconductor package, and more particularly, a lamination layer type semiconductor package capable of maintaining a thickness of a package on package structure at a minimum and minimizing a warpage defect by mounting two chips so as to correspond to each other. The lamination layer type semiconductor package includes: an upper package having an upper flip chip mounted on an upper substrate; a lower package having a lower flip chip mounted on a lower substrate and disposed so as to closely adhere the upper flip chip and the lower flip chip to each other; a heat dissipation adhesive member adhesively fixing the upper flip chip and the lower flip chip and dissipating heat generated from the upper flip chip and the lower flip chip; and a molding member molding between the upper substrate and the lower substrate.

    摘要翻译: 本文公开了一种叠层型半导体封装,更具体地说,是一种能够将封装结构上的封装的厚度最小化并且通过安装两个芯片以使彼此对应来最小化翘曲缺陷的层压层型半导体封装 。 叠层型半导体封装包括:上封装,其具有安装在上基板上的上倒装芯片; 下封装,其具有安装在下基板上的下倒装芯片,并且被设置为将上倒装芯片和下倒装芯片彼此紧贴; 散热粘合构件,其粘合地固定所述上倒装芯片和所述下倒装芯片,并消散由所述上倒装芯片和所述下倒装芯片产生的热量; 以及在上基板和下基板之间成型的成型部件。