Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal.