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    Delay locked loop and method of generating clock
    2.
    发明授权
    Delay locked loop and method of generating clock 有权
    延迟锁定环和产生时钟的方法

    公开(公告)号：US09035684B2

    公开(公告)日：2015-05-19

    申请号：US14157877

    申请日：2014-01-17

    申请人： Industry-Academic Cooperation Foundation, Yonsei University

    发明人： Seong-Ook Jung ,  Dong-Hoon Jung ,  Kyungho Ryu ,  Jung-Hyun Park

    IPC分类号： H03L7/06 ,  H03L7/08

    CPC分类号： H03L7/0802 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/16

    摘要： Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal.

    摘要翻译： 提供了一种包括环路振荡器（RO）的延迟锁定环路（DLL），该环路振荡器（RO）包括用于延迟参考时钟信号并产生延迟的时钟信号的延迟线，其中RO通过延迟线循环与 延迟时钟信号以使反馈时钟信号的N个周期与参考时钟信号（其中N是等于或大于2的整数）的周期同步; 以及将延迟时钟信号的频率除以1 / N（其中N是等于或大于2的整数）的第一分频器，以产生输出时钟信号。

    DELAY LOCKED LOOP AND METHOD OF GENERATING CLOCK
    3.
    发明申请
    DELAY LOCKED LOOP AND METHOD OF GENERATING CLOCK 有权
    延迟锁定环和产生时钟的方法

    公开(公告)号：US20140203854A1

    公开(公告)日：2014-07-24

    申请号：US14157877

    申请日：2014-01-17

    申请人： Industry-Academic Cooperation Foundation, Yonsei University

    发明人： Seong-Ook Jung ,  Dong-Hoon Jung ,  Kyungho Ryu ,  Jung-Hyun Park

    IPC分类号： H03L7/08

    CPC分类号： H03L7/0802 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/16

    摘要： Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal.

    摘要翻译： 提供了一种包括环路振荡器（RO）的延迟锁定环路（DLL），该环路振荡器（RO）包括用于延迟参考时钟信号并产生延迟的时钟信号的延迟线，其中RO通过延迟线循环与 延迟时钟信号以使反馈时钟信号的N个周期与参考时钟信号（其中N是等于或大于2的整数）的周期同步; 以及将延迟时钟信号的频率除以1 / N（其中N是等于或大于2的整数）的第一分频器，以产生输出时钟信号。

    Delay locked loop
    4.
    发明授权
    Delay locked loop 有权
    延迟锁定环路

    公开(公告)号：US08547153B2

    公开(公告)日：2013-10-01

    申请号：US13679045

    申请日：2012-11-16

    申请人： Industry-Academic Cooperation Foundation, Yonsei University

    发明人： Seongook Jung ,  Jung-Hyun Park ,  Kyung Ho Ryu ,  Dong Hun Jung

    IPC分类号： H03L7/06

    CPC分类号： H03L7/00 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/087

    摘要： A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal.

    摘要翻译： 根据本发明构思的一些实施例的延迟锁定环可以包括延迟信号生成部分，其通过基于延迟控制来延迟参考信号来生成具有第一相位的第一延迟信号和具有第二相位的第二延迟信号 信号; 使用第一延迟信号和第二延迟信号产生具有第三相的至少一个第三信号的相位合成部分; 以及相位检测部分，通过将参考信号与第一延迟信号，第二延迟信号和第三信号中的每一个进行比较来产生控制码。

    Time-to-digital converter
    5.
    发明授权
    Time-to-digital converter 有权
    时间到数字转换器

    公开(公告)号：US09104181B1

    公开(公告)日：2015-08-11

    申请号：US14690220

    申请日：2015-04-17

    申请人： Industry-Academic Cooperation Foundation, Yonsei University

    发明人： Seongook Jung ,  Jung-Hyun Park ,  Kyung Ho Ryu ,  Dong Hun Jung

    IPC分类号： H03M1/50 ,  G04F10/00 ,  H03M1/08 ,  H03M1/12 ,  H03L7/089 ,  H03M1/00

    CPC分类号： G04F10/005 ,  H03L7/0891 ,  H03L7/0895 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M2201/4233

    摘要： A time-to-digital converter includes a first gated ring oscillator, a second gated ring oscillator, a phase adjusting unit, and a digital converter unit. The first gated ring oscillator includes a plurality of first delay cells connected in a cyclic structure and operating in response to an enable signal. The second gated ring oscillator includes a plurality of second delay cells connected in a cyclic structure and operating in response to the enable signal. The phase adjusting unit adjusts a phase of a second circulation signal circulating in the second gated ring oscillator so as for the second circulation signal to have a predetermined phase difference with respect to a first circulation signal circulating in the first gated ring oscillator. The digital converter unit samples output signals of the first delay cells and the second delay cells to output a digital value corresponding to duration of the enable signal.

    摘要翻译： 时 - 数转换器包括第一门控环形振荡器，第二门控环形振荡器，相位调整单元和数字转换器单元。 第一选通环形振荡器包括以循环结构连接并响应于使能信号而工作的多个第一延迟单元。 第二选通环形振荡器包括以循环结构连接并响应于使能信号而工作的多个第二延迟单元。 相位调整单元调节在第二选通环形振荡器中循环的第二循环信号的相位，使得第二循环信号相对于在第一选通环形振荡器中循环的第一循环信号具有预定的相位差。 数字转换器单元对第一延迟单元和第二延迟单元的输出信号进行采样，以输出对应于使能信号的持续时间的数字值。