Invention Application
- Patent Title: III-NITRIDE TRANSISTOR LAYOUT
- Patent Title (中): III-NITRIDE晶体管布局
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Application No.: US13886429Application Date: 2013-05-03
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Publication No.: US20140327011A1Publication Date: 2014-11-06
- Inventor: Sameer PENDHARKAR , Naveen TIPIRNENI , Jungwoo JOH
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: H01L29/20
- IPC: H01L29/20

Abstract:
A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.
Public/Granted literature
- US09054027B2 III-nitride device and method having a gate isolating structure Public/Granted day:2015-06-09
Information query
IPC分类: