公开(公告)号：US20230101610A1

公开(公告)日：2023-03-30

申请号：US17490918

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Meng-Chia LEE ,  Sunglyong KIM ,  Seetharaman SRIDHAR ,  Sameer PENDHARKAR

IPC: H01L29/78

Abstract: An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

公开(公告)号：US20190011493A1

公开(公告)日：2019-01-10

申请号：US16130035

申请日：2018-09-13

Applicant: Texas Instruments Incorporated

Inventor： Alex PAIKIN ,  Colin JOHNSON ,  Tathagata CHATTERJEE ,  Sameer PENDHARKAR

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2628 ,  G01R31/2642 ,  G01R31/2849

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

公开(公告)号：US20150270357A1

公开(公告)日：2015-09-24

申请号：US14731744

申请日：2015-06-05

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/20 ,  H01L27/085 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。

公开(公告)号：US20140339671A1

公开(公告)日：2014-11-20

申请号：US14450784

申请日：2014-08-04

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/40 ,  H01L21/311

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract translation: 半导体器件在至少三个连续区域上形成有台阶式场板，其中在阶梯式场板下的总电介质厚度与先前区域相比在每个区域中至少为10％以上。 各区域的总电介质厚度均匀。 阶梯式场板形成在至少两个电介质层上，至少两个电介质层至少形成一个电介质层，使得图案化的电介质层的至少一部分在阶梯式场板的一个或多个区域中被去除。

公开(公告)号：US20140183631A1

公开(公告)日：2014-07-03

申请号：US14101442

申请日：2013-12-10

Applicant: Texas Instruments Incorporated

Inventor： Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7835

Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

Abstract translation: 包含模拟MOS晶体管的集成电路具有用于阱的注入掩模，该掩模从栅极边缘处的两个稀释区域阻挡良好的掺杂剂，但是将沟道区域暴露于阱掺杂剂。 热驱动步骤将注入的阱掺杂物扩散到两个稀释区域上以在两个稀释区域中形成具有较低掺杂密度的连续阱。 通过使用栅极作为阻挡层将源极/漏极掺杂剂注入邻近栅极的衬底中，形成栅/漏区邻近并且使其重叠，随后使衬底退火，使得注入的源极/漏极掺杂剂提供期望的程度 栅极下的源极/漏极区的叠加。 漏极延伸掺杂剂和卤素掺杂剂不会被注入到与栅极相邻的衬底中。

公开(公告)号：US20250063755A1

公开(公告)日：2025-02-20

申请号：US18937600

申请日：2024-11-05

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer, and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20190157091A1

公开(公告)日：2019-05-23

申请号：US16163602

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup LEE ,  Yoshikazu KONDO ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

公开(公告)号：US20180151713A1

公开(公告)日：2018-05-31

申请号：US15864157

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo JOH ,  Naveen TIPIRNENI ,  Chang Soo SUH ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L21/308 ,  H01L21/266

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20170084737A1

公开(公告)日：2017-03-23

申请号：US15364817

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/324 ,  H01L29/36 ,  H01L21/266 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

公开(公告)号：US20160300946A1

公开(公告)日：2016-10-13

申请号：US15182658

申请日：2016-06-15

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.