公开(公告)号：US20140327011A1

公开(公告)日：2014-11-06

申请号：US13886429

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/20

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。

公开(公告)号：US20200287033A1

公开(公告)日：2020-09-10

申请号：US16294687

申请日：2019-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo SUH ,  Sameer Prakash PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/417 ,  H01L29/423

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US20150270357A1

公开(公告)日：2015-09-24

申请号：US14731744

申请日：2015-06-05

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/20 ,  H01L27/085 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。

公开(公告)号：US20200303535A1

公开(公告)日：2020-09-24

申请号：US16895111

申请日：2020-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo JOH ,  Naveen TIPIRNENI ,  Chang Soo SUH ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20140327047A1

公开(公告)日：2014-11-06

申请号：US13886744

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Asad Mahmood HAIDER ,  Jungwoo JOH

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66462

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract translation: 可以通过在半导体层上形成含硅栅极电介质层来形成半导体器件。 栅极金属层形成在栅极介质层上; 栅极金属层在形成期间包括2原子％至10原子％的硅。 栅极金属层被图案化以形成金属栅极。 随后形成源极和漏极接触孔，并在接触孔中形成接触金属并图案化。 随后的接触退火在至少750℃的温度下加热接触金属和栅极至少30秒。

公开(公告)号：US20250063755A1

公开(公告)日：2025-02-20

申请号：US18937600

申请日：2024-11-05

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer, and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20180151713A1

公开(公告)日：2018-05-31

申请号：US15864157

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo JOH ,  Naveen TIPIRNENI ,  Chang Soo SUH ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L21/308 ,  H01L21/266

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20230369482A1

公开(公告)日：2023-11-16

申请号：US18357431

申请日：2023-07-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L21/265 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7786 ,  H01L29/41775 ,  H01L29/0843 ,  H01L29/0603 ,  H01L21/2654 ,  H01L29/2003 ,  H01L21/26546 ,  H01L29/66462 ,  H01L29/66431 ,  H01L29/0607 ,  H01L29/42316 ,  H01L29/0891

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20210280702A1

公开(公告)日：2021-09-09

申请号：US17330012

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo SUH ,  Sameer Prakash PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L21/308 ,  H01L29/417 ,  H01L21/02

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US20210159329A1

公开(公告)日：2021-05-27

申请号：US17165697

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L29/417

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.