Invention Application
US20140328115A1 POSITIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
有权
正向边缘预置位复位带双口自动锁定的浮动片
- Patent Title: POSITIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
- Patent Title (中): 正向边缘预置位复位带双口自动锁定的浮动片
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Application No.: US13973274Application Date: 2013-08-22
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Publication No.: US20140328115A1Publication Date: 2014-11-06
- Inventor: Steven Bartling , Sudhanshu Khanna
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Main IPC: H03K3/3562
- IPC: H03K3/3562 ; G11C11/419

Abstract:
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
Public/Granted literature
- US09099998B2 Positive edge preset reset flip-flop with dual-port slave latch Public/Granted day:2015-08-04
Information query
IPC分类: