公开(公告)号：US10409607B2

公开(公告)日：2019-09-10

申请号：US14739236

申请日：2015-06-15

Applicant: Texas Instruments Incorporated

Inventor： Marko Krüger ,  Steven Bartling ,  Markus Kösler

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3237

Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.

公开(公告)号：US20140347114A1

公开(公告)日：2014-11-27

申请号：US14457310

申请日：2014-08-12

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/012 ,  H03K3/289

CPC classification number: H03K3/012 ,  H03K3/289 ,  H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否被锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20200073667A1

公开(公告)日：2020-03-05

申请号：US16564652

申请日：2019-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marko Krüger ,  Steven Bartling ,  Markus Kösler

IPC: G06F9/38 ,  G06F1/3237 ,  G06F9/30

Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.

公开(公告)号：US20140232442A1

公开(公告)日：2014-08-21

申请号：US14154458

申请日：2014-01-14

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/3562

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SS，RE和REN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140232441A1

公开(公告)日：2014-08-21

申请号：US13948901

申请日：2013-07-23

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US09099998B2

公开(公告)日：2015-08-04

申请号：US13973274

申请日：2013-08-22

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/289 ,  H03K3/3562 ,  G11C11/419

CPC classification number: H03K3/35625 ,  G11C11/419

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US09088271B2

公开(公告)日：2015-07-21

申请号：US14035250

申请日：2013-09-24

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/356 ,  H03K3/037

CPC classification number: H03K3/0375

Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal (CKT) goes high, (CLKZ) goes low and retention control signal is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit (D2), the clock signals (CKT) and (CLKN), the retain control signals (RET) and the control signals SS (SS) and (SSN). The signals (CKT), (CLKZ), (RET), (SS) and (SSN) determine whether the output of the clocked inverter or the second data bit (D2) is latched in the dual-port latch. Control signal (RET) determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口正电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号（CKT）变高，（CLKZ）变为低电平，保持控制信号为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位（D2），时钟信号（CKT）和（CLKN），保持控制信号（RET）和控制信号SS（SS） 和（SSN）。 信号（CKT），（CLKZ），（RET），（SS）和（SSN）确定时钟反相器或第二数据位（D2）的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号（RET）确定数据何时存储在双端口锁存器中。

公开(公告)号：US20150042390A1

公开(公告)日：2015-02-12

申请号：US14035250

申请日：2013-09-24

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口正电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和控制信号SS和SSN。 信号CKT，CLKZ，RET，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

公开(公告)号：US08836399B2

公开(公告)日：2014-09-16

申请号：US13759249

申请日：2013-02-05

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/289 ,  H03K3/012

CPC classification number: H03K3/3562 ,  G01R31/318541 ,  H03K3/012 ,  H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140232439A1

公开(公告)日：2014-08-21

申请号：US14154586

申请日：2014-01-14

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/3562

CPC classification number: H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN RE, and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN RE和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。