Invention Application
US20140328196A1 TIME EFFICIENT COUNTERS AND METERS ARCHITECTURE 有权
时间有效的计数器和仪表架构

TIME EFFICIENT COUNTERS AND METERS ARCHITECTURE
Abstract:
A network device includes a plurality of interfaces configured to receive, from a network, packets to be processed by the network device. A load determination circuit of the network device is configured to determine whether a packet traffic load of the network device is above a traffic load threshold, and a dual-mode counter module is configured to (i) determine a count of quanta associated with the received packets using a first counting mode in response to the load determination unit determining that the packet traffic load is above the traffic load threshold, and (ii) determine a count of quanta associated with the received packets using a second counting mode, different than the first counting mode, in response to the load determination unit determining that the packet traffic load is not above the traffic load threshold.
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