Time efficient counters and meters architecture

    公开(公告)号:US10333802B2

    公开(公告)日:2019-06-25

    申请号:US15722601

    申请日:2017-10-02

    Abstract: A meter module for use in a network device comprises conformance circuitry configured to: access a first memory device storing a conformance indicator that indicates whether a permitted rate of packet traffic has been exceeded, and classify packets received at the network device based at least in part on the conformance indicator. Sampling circuitry is configured to, responsively to the conformance circuitry classifying the packets: sample events associated with at least some of the received packets, and generate indicators of the sampled events. Update circuitry is configured to: access a second memory device, slower than the first memory, to update a number of tokens stored in the second memory device, and access the first memory device to update the conformance indicator when the updated number of tokens indicates that the permitted rate of packet traffic has been exceeded.

    Time efficient counters and meters architecture

    公开(公告)号:US09781018B2

    公开(公告)日:2017-10-03

    申请号:US14269664

    申请日:2014-05-05

    Abstract: A network device includes a plurality of interfaces configured to receive, from a network, packets to be processed by the network device. A load determination circuit of the network device is configured to determine whether a packet traffic load of the network device is above a traffic load threshold, and a dual-mode counter module is configured to (i) determine a count of quanta associated with the received packets using a first counting mode in response to the load determination unit determining that the packet traffic load is above the traffic load threshold, and (ii) determine a count of quanta associated with the received packets using a second counting mode, different than the first counting mode, in response to the load determination unit determining that the packet traffic load is not above the traffic load threshold.

    SEMAPHORE SOFT AND HARD HYBRID ARCHITECTURE
    3.
    发明申请

    公开(公告)号:US20140233582A1

    公开(公告)日:2014-08-21

    申请号:US13973744

    申请日:2013-08-22

    CPC classification number: H04L45/44 H04L45/00 H04L45/121 H04L49/00

    Abstract: A packet processing device has a plurality of processing stages, including a first processing stage and a second processing stage arranged as a packet processing pipeline. The first processing stage and the second processing stage each have a respective processor configured to process a packet of a packet stream and a respective resource manager having a respective local resource lock corresponding to a remote resource. The respective processor requests the respective resource manager to allocate the remote resource. The respective resource manager responds to the request to allocate the remote resource by locking the remote resource with the respective local resource lock and allocating the remote resource. The respective processor implements a packet processing operation associated with the allocated remote resource.

    TIME EFFICIENT COUNTERS AND METERS ARCHITECTURE
    4.
    发明申请
    TIME EFFICIENT COUNTERS AND METERS ARCHITECTURE 有权
    时间有效的计数器和仪表架构

    公开(公告)号:US20140328196A1

    公开(公告)日:2014-11-06

    申请号:US14269664

    申请日:2014-05-05

    Abstract: A network device includes a plurality of interfaces configured to receive, from a network, packets to be processed by the network device. A load determination circuit of the network device is configured to determine whether a packet traffic load of the network device is above a traffic load threshold, and a dual-mode counter module is configured to (i) determine a count of quanta associated with the received packets using a first counting mode in response to the load determination unit determining that the packet traffic load is above the traffic load threshold, and (ii) determine a count of quanta associated with the received packets using a second counting mode, different than the first counting mode, in response to the load determination unit determining that the packet traffic load is not above the traffic load threshold.

    Abstract translation: 网络设备包括被配置为从网络接收要由网络设备处理的分组的多个接口。 网络设备的负载确定电路被配置为确定网络设备的分组业务负载是否高于业务负载阈值,并且双模计数器模块被配置为(i)确定与所接收的相关联的量子的计数 响应于负载确定单元确定分组业务负载高于业务负载阈值,并且(ii)使用与第一计数模式不同的第二计数模式来确定与所接收的分组相关联的量化的计数, 计数模式,响应于负载确定单元确定分组业务负载不高于业务负载阈值。

    Semaphore soft and hard hybrid architecture
    5.
    发明授权
    Semaphore soft and hard hybrid architecture 有权
    信号量软硬混合架构

    公开(公告)号:US09525621B2

    公开(公告)日:2016-12-20

    申请号:US13973751

    申请日:2013-08-22

    CPC classification number: H04L45/44 H04L45/00 H04L45/121 H04L49/00

    Abstract: A packet processing device has a plurality of processing stages, including a first processing stage and a second processing stage arranged as a packet processing pipeline. The first processing stage and the second processing stage each have a respective processor configured to process a packet of a packet stream and a respective resource manager having a respective local resource lock corresponding to a remote resource. The respective processor requests the respective resource manager to allocate the remote resource. The respective resource manager responds to the request to allocate the remote resource by locking the remote resource with the respective local resource lock and allocating the remote resource. The respective processor implements a packet processing operation associated with the allocated remote resource.

    Abstract translation: 分组处理装置具有多个处理级,包括布置为分组处理流水线的第一处理阶段和第二处理阶段。 第一处理阶段和第二处理阶段各自具有被配置为处理分组流的分组的相应处理器和具有与远程资源相对应的相应本地资源锁定的相应资源管理器。 相应的处理器请求相应的资源管理器分配远程资源。 相应的资源管理器通过使用相应的本地资源锁定锁定远程资源并分配远程资源来响应分配远程资源的请求。 相应的处理器实现与所分配的远程资源相关联的分组处理操作。

    Method and apparatus for internal/external memory packet and byte counting
    6.
    发明授权
    Method and apparatus for internal/external memory packet and byte counting 有权
    用于内部/外部存储器分组和字节计数的方法和装置

    公开(公告)号:US08995263B2

    公开(公告)日:2015-03-31

    申请号:US13898942

    申请日:2013-05-21

    CPC classification number: H04L49/9084 H04L49/9078

    Abstract: Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.

    Abstract translation: 提供了系统和方法,用于对接收到的数据包的数量和包含在接收数据包中的字节数进行计数。 一种系统包括设置在集成电路中的第一存储器,所述第一存储器被配置为具有用于存储接收到的分组的小计的第一组位的第一组合计数器,以及用于存储包含在 收到的数据包。 第二个存储器是集成电路的外部。 第二存储器被配置为存储接收到的分组的总数和包含在接收分组中的总字节数。 更新电路被配置为当第一存储器中的第一组位或第二组位中的任何一个溢出时,更新存储在第二存储器中的分组的总数。

    Hybrid dataflow processor
    7.
    发明授权
    Hybrid dataflow processor 有权
    混合数据流处理器

    公开(公告)号:US09294410B2

    公开(公告)日:2016-03-22

    申请号:US13891707

    申请日:2013-05-10

    CPC classification number: H04L47/24 H04L47/39

    Abstract: A network device that processes a stream of packets has an ingress front end. The ingress front end determines whether the packets are handled in a bounded latency path or in a best-effort path. The bounded latency path packets are granted a resource with a higher priority than the best-effort path packets. As the packets are processed through a number of processing stages, with processing engines, the bounded latency packets are processed within a period of time corresponding to a guaranteed rate. Resources are granted to the best-effort path packets only when the processing engines determine that the resource grant will not impact the latency bounds with respect to the first packets.

    Abstract translation: 处理数据包流的网络设备具有入口前端。 入口前端确定数据包是否在有界的等待时间路径或尽力而为的路径中处理。 有限延迟路径数据包被授予比尽力而为路径数据包更高优先级的资源。 当通过多个处理阶段对数据包进行处理时,利用处理引擎,有界延迟分组在对应于保证速率的时间段内被处理。 只有当处理引擎确定资源授权不会影响相对于第一个数据包的延迟范围时,才会将资源授予尽力而为的路径数据包。

    SEMAPHORE SOFT AND HARD HYBRID ARCHITECTURE
    8.
    发明申请
    SEMAPHORE SOFT AND HARD HYBRID ARCHITECTURE 有权
    SEMAPHORE软硬混合建筑

    公开(公告)号:US20140064271A1

    公开(公告)日:2014-03-06

    申请号:US13973751

    申请日:2013-08-22

    CPC classification number: H04L45/44 H04L45/00 H04L45/121 H04L49/00

    Abstract: A packet processing device has a plurality of processing stages, including a first processing stage and a second processing stage arranged as a packet processing pipeline. The first processing stage and the second processing stage each have a respective processor configured to process a packet of a packet stream and a respective resource manager having a respective local resource lock corresponding to a remote resource. The respective processor requests the respective resource manager to allocate the remote resource. The respective resource manager responds to the request to allocate the remote resource by locking the remote resource with the respective local resource lock and allocating the remote resource. The respective processor implements a packet processing operation associated with the allocated remote resource.

    Abstract translation: 分组处理装置具有多个处理级,包括布置为分组处理流水线的第一处理阶段和第二处理阶段。 第一处理阶段和第二处理阶段各自具有被配置为处理分组流的分组的相应处理器和具有与远程资源相对应的相应本地资源锁定的相应资源管理器。 相应的处理器请求相应的资源管理器分配远程资源。 相应的资源管理器通过使用相应的本地资源锁定锁定远程资源并分配远程资源来响应分配远程资源的请求。 相应的处理器实现与所分配的远程资源相关联的分组处理操作。

    Method and Apparatus for Internal/External Memory Packet and Byte Counting
    9.
    发明申请
    Method and Apparatus for Internal/External Memory Packet and Byte Counting 有权
    内部/外部存储器包和字节计数的方法和装置

    公开(公告)号:US20130315259A1

    公开(公告)日:2013-11-28

    申请号:US13898942

    申请日:2013-05-21

    CPC classification number: H04L49/9084 H04L49/9078

    Abstract: Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.

    Abstract translation: 提供了系统和方法,用于对接收到的数据包的数量和包含在接收数据包中的字节数进行计数。 一种系统包括设置在集成电路中的第一存储器,所述第一存储器被配置为具有用于存储接收到的分组的小计的第一组位的第一组合计数器,以及用于存储包含在 收到的数据包。 第二个存储器是集成电路的外部。 第二存储器被配置为存储接收到的分组的总数和包含在接收分组中的总字节数。 更新电路被配置为当第一存储器中的第一组位或第二组位中的任何一个溢出时,更新存储在第二存储器中的分组的总数。

    HYBRID DATAFLOW PROCESSOR
    10.
    发明申请
    HYBRID DATAFLOW PROCESSOR 有权
    混合数据流处理器

    公开(公告)号:US20130301408A1

    公开(公告)日:2013-11-14

    申请号:US13891707

    申请日:2013-05-10

    CPC classification number: H04L47/24 H04L47/39

    Abstract: A network device that processes a stream of packets has an ingress front end. The ingress front end determines whether the packets are handled in a bounded latency path or in a best-effort path. The bounded latency path packets are granted a resource with a higher priority than the best-effort path packets. As the packets are processed through a number of processing stages, with processing engines, the bounded latency packets are processed within a period of time corresponding to a guaranteed rate. Resources are granted to the best-effort path packets only when the processing engines determine that the resource grant will not impact the latency bounds with respect to the first packets.

    Abstract translation: 处理数据包流的网络设备具有入口前端。 入口前端确定数据包是否在有界的等待时间路径或尽力而为的路径中处理。 有限延迟路径数据包被授予比尽力而为路径数据包更高优先级的资源。 当通过多个处理阶段对数据包进行处理时,利用处理引擎,有界延迟分组在对应于保证速率的时间段内被处理。 只有当处理引擎确定资源授权不会影响相对于第一个数据包的延迟范围时,才会将资源授予尽力而为的路径数据包。

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