发明申请
US20150147882A1 Integrated Circuits with Reduced Pitch and Line Spacing and Methods of Forming the Same 有权
具有减小间距和线间距的集成电路及其形成方法

Integrated Circuits with Reduced Pitch and Line Spacing and Methods of Forming the Same
摘要:
A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the second mandrel being between the first mandrel and the second mandrel, and etching the second mandrel to cut the second mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the mandrel, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.
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