公开(公告)号：US11222826B2

公开(公告)日：2022-01-11

申请号：US16685758

申请日：2019-11-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chun Huang ,  Chih-Tang Peng ,  Kuang-Yuan Hsu ,  Tai-Chun Huang ,  Tsu-Hsiu Perng ,  Tien-I Bao

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L27/088

摘要： A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

公开(公告)号：US20210366726A1

公开(公告)日：2021-11-25

申请号：US17397756

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/522

摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US20210098362A1

公开(公告)日：2021-04-01

申请号：US17120601

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Hsu Wu ,  Hai-Ching Chen ,  Jung-Hsun Tsai ,  Shau-Lin Shue ,  Tien-I Bao

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

摘要： A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

公开(公告)号：US20210043569A1

公开(公告)日：2021-02-11

申请号：US17080051

申请日：2020-10-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

摘要： A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

公开(公告)号：US10784160B2

公开(公告)日：2020-09-22

申请号：US16390715

申请日：2019-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Hsu Wu ,  Chien-Hua Huang ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.

公开(公告)号：US10679846B2

公开(公告)日：2020-06-09

申请号：US16016804

申请日：2018-06-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/52 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528

摘要： The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

公开(公告)号：US10665467B2

公开(公告)日：2020-05-26

申请号：US15357203

申请日：2016-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ru-Gun Liu ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Chih-Ming Lai ,  Chia-Ying Lee ,  Jyu-Horng Shieh ,  Ken-Hsien Hsieh ,  Ming-Feng Shieh ,  Shau-Lin Shue ,  Shih-Ming Chang ,  Tien-I Bao ,  Tsai-Sheng Gau

IPC分类号： H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105

摘要： A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.

公开(公告)号：US10483169B2

公开(公告)日：2019-11-19

申请号：US15280703

申请日：2016-09-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chun Huang ,  Chih-Tang Peng ,  Kuang-Yuan Hsu ,  Tai-Chun Huang ,  Tsu-Hsiu Perng ,  Tien-I Bao

IPC分类号： H01L21/8234 ,  H01L21/762

摘要： A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

公开(公告)号：US20190287848A1

公开(公告)日：2019-09-19

申请号：US16429111

申请日：2019-06-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Shau-Lin Shue ,  Tien-I Bao

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528

摘要： A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.

公开(公告)号：US10408998B2

公开(公告)日：2019-09-10

申请号：US15911403

申请日：2018-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/13 ,  G02B6/12 ,  G02B6/138 ,  G02B6/132 ,  G02B6/136 ,  F21V8/00 ,  G02B6/42

摘要： A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.