公开(公告)号：US12249555B2

公开(公告)日：2025-03-11

申请号：US17380360

申请日：2021-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Chin Lee ,  Cherng-Shiaw Tsai ,  Shao-Kuan Lee ,  Hsiao-kang Chang ,  Hsin-Yen Huang ,  Shau-Lin Shue

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure. The second thermal feature is in contact with the first thermal feature.

公开(公告)号：US12230537B2

公开(公告)日：2025-02-18

申请号：US18230338

申请日：2023-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Ya Lo ,  Cheng-Chin Lee ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions. The method includes forming a capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the first conductive layer, forming a sacrificial layer in the one or more openings, recessing the sacrificial layer, forming a support layer on the recessed sacrificial layer in each of the one or more openings, removing the sacrificial layer to form an air gap in each of the one or more openings, forming a dielectric fill on the support layer, replacing the first conductive layer in the one or more openings with a second conductive layer, selectively forming a two-dimensional (2D) material layer on the second conductive layer, forming a first etch stop layer on the dielectric fill and the support layer, forming a second etch stop layer on the first etch stop layer and the 2D material layer, forming a dielectric material on the second etch stop layer, forming a contact opening through the dielectric material, the second etch stop layer, and the 2D material layer to expose a top surface of the second conductive layer, and forming a first conductive feature in the contact opening.

公开(公告)号：US12211788B2

公开(公告)日：2025-01-28

申请号：US18340079

申请日：2023-06-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.

公开(公告)号：US12132000B2

公开(公告)日：2024-10-29

申请号：US17460168

申请日：2021-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Cherng-Shiaw Tsai ,  Kuang-Wei Yang ,  Hsin-Yen Huang ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/53276 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/535 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.

公开(公告)号：US12094848B2

公开(公告)日：2024-09-17

申请号：US17383355

申请日：2021-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/24 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/24137

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through a RDL structure formed between the two or more integrated circuit dies.

公开(公告)号：US12074060B2

公开(公告)日：2024-08-27

申请号：US17460173

申请日：2021-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Chin Lee ,  Shao-Kuan Lee ,  Kuang-Wei Yang ,  Cherng-Shiaw Tsai ,  Hsin-Yen Huang ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76837 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature, a first liner having a first top surface disposed on the first conductive feature, a second conductive feature disposed adjacent the first conductive feature, and a second liner disposed on at least a portion of the second conductive feature. The second liner has a second top surface, and the first liner and the second liner each comprises a two-dimensional material. The structure further includes a first dielectric material disposed between the first and second conductive features and a dielectric layer disposed on the first dielectric material. The dielectric layer has a third top surface, and the first, second, and third top surfaces are substantially co-planar.

公开(公告)号：US20240178002A1

公开(公告)日：2024-05-30

申请号：US18433251

申请日：2024-02-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/823481 ,  H01L21/823878

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

公开(公告)号：US11972975B2

公开(公告)日：2024-04-30

申请号：US17356959

申请日：2021-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Chieh Yao ,  Chih-Wei Lu ,  Chung-Ju Lee ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

公开(公告)号：US20240136221A1

公开(公告)日：2024-04-25

申请号：US18403044

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Kuan Lee ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Cheng-Chin Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76829 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

公开(公告)号：US11810815B2

公开(公告)日：2023-11-07

申请号：US17729429

申请日：2022-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/764

CPC classification number: H01L21/7682 ,  H01L23/5329 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53295

Abstract: Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.