公开(公告)号：US11640940B2

公开(公告)日：2023-05-02

申请号：US17314269

申请日：2021-05-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Wei Li ,  Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532

摘要： An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. The first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. The structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. Each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. The structure further includes a dielectric material disposed between the first and second portions of the conductive layer.

公开(公告)号：US11640928B2

公开(公告)日：2023-05-02

申请号：US17412423

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Shau-Lin Shue ,  Hsiao-Kang Chang ,  Cherng-Shiaw Tsai

IPC分类号： H01L21/48 ,  H01L23/48 ,  H01L23/52 ,  H01L23/367 ,  H01L23/522 ,  H01L23/373

摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.

公开(公告)号：US11557511B2

公开(公告)日：2023-01-17

申请号：US17146821

申请日：2021-01-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

公开(公告)号：US20220415798A1

公开(公告)日：2022-12-29

申请号：US17355566

申请日：2021-06-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Wei Li ,  Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/535 ,  H01L21/02 ,  H01L21/768

摘要： The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

公开(公告)号：US20220359385A1

公开(公告)日：2022-11-10

申请号：US17873214

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Cheng-Chin Lee ,  Kuang-Wei Yang ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.

公开(公告)号：US11482451B2

公开(公告)日：2022-10-25

申请号：US16949953

申请日：2020-11-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guanyu Luo ,  Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45 ,  H01L23/522

摘要： A method includes receiving an integrated circuit (IC) layout having a plurality of metal features in a metal layer. The method also includes classifying the plurality of metal features into a first type of metal features and a second type of metal features based on a dimensional criterion, where the first type of the metal features have dimensions greater than the second type of the metal features. The method further includes assigning to the first type of metal features a first metal material, and to the second type of metal features a second metal material, where the second metal material is different from the first metal material. The method additionally includes forming the plurality of metal features embedded within a dielectric layer, where each of the plurality of metal features have the respective assigned metal materials.

公开(公告)号：US11387113B2

公开(公告)日：2022-07-12

申请号：US17080248

申请日：2020-10-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238

摘要： A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

公开(公告)号：US20210366726A1

公开(公告)日：2021-11-25

申请号：US17397756

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/522

摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

公开(公告)号：US20210098362A1

公开(公告)日：2021-04-01

申请号：US17120601

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Hsu Wu ,  Hai-Ching Chen ,  Jung-Hsun Tsai ,  Shau-Lin Shue ,  Tien-I Bao

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

摘要： A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

公开(公告)号：US20210057231A1

公开(公告)日：2021-02-25

申请号：US17080248

申请日：2020-10-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768

摘要： A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.