Invention Application
- Patent Title: 1D-2R MEMORY ARCHITECTURE
- Patent Title (中): 1D-2R存储器架构
-
Application No.: US14568011Application Date: 2014-12-11
-
Publication No.: US20150162382A1Publication Date: 2015-06-11
- Inventor: Deepak Chandra Sekar , Gary Bela Bronner , Christophe J. Chevallier , Lidia Vereen , Philip F.S. Swab , Elizabeth Friend , Mehmet Gunhan Ertosun
- Applicant: Rambus Inc.
- Main IPC: H01L27/24
- IPC: H01L27/24 ; G11C13/00
Abstract:
A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.
Public/Granted literature
- US09570165B2 1D-2R memory architecture Public/Granted day:2017-02-14
Information query
IPC分类:
