中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.012 seconds)

    FAST READ SPEED MEMORY DEVICE
    2.
    发明申请
    FAST READ SPEED MEMORY DEVICE 有权
    快速读速度存储器件

    公开(公告)号：US20140269006A1

    公开(公告)日：2014-09-18

    申请号：US14210085

    申请日：2014-03-13

    Applicant: Rambus Inc.

    Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

    Abstract: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node.

    Abstract translation: 存储器件包括电阻存储器单元阵列。 阵列中的每个电阻性存储单元包括第一电阻性存储器元件，第二电阻性存储器元件，其与第一电阻性存储器元件电连接在第一电阻性存储器元件的第一端子与第二电阻性存储器的第一端子之间的公共节点处 元件，以及包括与公共节点电耦合的栅极的晶体管。

    CONTENT ADDRESSABLE MEMORY
    5.
    发明申请
    CONTENT ADDRESSABLE MEMORY 有权
    内容可寻址内存

    公开(公告)号：US20140153310A1

    公开(公告)日：2014-06-05

    申请号：US14091213

    申请日：2013-11-26

    Applicant: Rambus Inc.

    Inventor： Deepak Chandra Sekar ,  Brent Steven Haukness ,  John Eric Linstadt ,  Scott C. Best

    IPC: G11C15/00 ,  G11C13/00

    CPC classification number: G11C15/00 ,  G11C13/0002 ,  G11C15/046

    Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

    Abstract translation: 内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。 诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。 在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。 匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。 内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。

    Reduced current memory device
    6.
    发明授权
    Reduced current memory device 有权

    公开(公告)号：US10658037B2

    公开(公告)日：2020-05-19

    申请号：US16209479

    申请日：2018-12-04

    Applicant: RAMBUS INC.

    Inventor： Deepak Chandra Sekar ,  Brent S. Haukness ,  Bruce L. Bateman

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00 ,  H01L27/24

    Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.

    Reduced current memory device
    9.
    发明授权
    Reduced current memory device 有权

    公开(公告)号：US10224100B2

    公开(公告)日：2019-03-05

    申请号：US15100167

    申请日：2014-12-03

    Applicant: RAMBUS INC.

    Inventor： Deepak Chandra Sekar ,  Brent S. Haukness ,  Bruce L. Bateman

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00 ,  H01L27/24

    Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.

Patent Agency Ranking