Invention Application
US20150304098A1 MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT
审中-公开
MULTILANE SERDES时钟和数据轴对齐多标准支持
- Patent Title: MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT
- Patent Title (中): MULTILANE SERDES时钟和数据轴对齐多标准支持
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Application No.: US14755127Application Date: 2015-06-30
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Publication No.: US20150304098A1Publication Date: 2015-10-22
- Inventor: Adesh Garg , Jun Cao , Namik Kocaman , Kuo-J (Nick) Huang , Delong Cui , Afshin Momtaz
- Applicant: Broadcom Corporation
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.
Public/Granted literature
- US10033520B2 Multilane serdes clock and data skew alignment for multi-standard support Public/Granted day:2018-07-24
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