公开(公告)号：US20150304098A1

公开(公告)日：2015-10-22

申请号：US14755127

申请日：2015-06-30

Applicant: Broadcom Corporation

Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J (Nick) Huang ,  Delong Cui ,  Afshin Momtaz

IPC: H04L7/00

CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

公开(公告)号：US08902094B1

公开(公告)日：2014-12-02

申请号：US14087457

申请日：2013-11-22

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao

IPC: H03M1/00 ,  H03M1/08 ,  H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H04L7/00 ,  H03K5/135 ,  H03L7/089

CPC classification number: H03M1/08 ,  H03K5/135 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H04L7/0008

Abstract: A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.

Abstract translation: 第一时钟发生器接收输入时钟，产生用于时间交织的模数转换器的多电平跟踪和保持电路的第一电平的第一时钟信号，并产生第一时钟信号的时间领先的版本。 多个第二时钟发生器接收输入时钟并产生对应的多个第二时钟信号，以在多电平跟踪和保持电路的第二电平中使用。 多个第二电平时钟发生器包括可调节的延迟，其延迟多个第二时钟信号中的相应一个第二时钟信号的延迟量，该延迟量基于延迟控制信号确定。 反馈控制器基于第一时钟信号的时间引导版本并且还基于多个第二时钟信号中的相应一个产生延迟控制信号。

公开(公告)号：US20150008982A1

公开(公告)日：2015-01-08

申请号：US14042274

申请日：2013-09-30

Applicant: Broadcom Corporation

Inventor： Kuo-J Huang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz ,  Iuri Mehr ,  Ramon Alejandro Gomez

IPC: H03F1/32

CPC classification number: H03F1/3205 ,  H03F1/3211 ,  H03F1/3241 ,  Y10T29/49016

Abstract: Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

Abstract translation: 这里描述了利用负增益自适应地抑制放大器中的谐波失真的技术。 放大器包括并联耦合的第一放大级和第二放大级。 第一个放大器级具有正增益。 第二放大器级具有负增益以抑制包括放大器的系统的总谐波失真。 放大器还包括耦合到第一放大器级和第二放大器级的并联峰值电路，以增加放大器能够操作的最大工作频率。

公开(公告)号：US09100167B2

公开(公告)日：2015-08-04

申请号：US13691482

申请日：2012-11-30

Applicant: Broadcom Corporation

Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

IPC: G06F1/04 ,  H04L7/033 ,  G06F1/10 ,  H04L25/14 ,  H04L7/00

CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

公开(公告)号：US20150084800A1

公开(公告)日：2015-03-26

申请号：US14040467

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03M1/12

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/1215

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

Abstract translation: 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。

公开(公告)号：US08928355B2

公开(公告)日：2015-01-06

申请号：US13867883

申请日：2013-04-22

Applicant: Broadcom Corporation

Inventor： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC: H03K19/094 ,  H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45

CPC classification number: H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03F2203/45706

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

Abstract translation: 为高速收发器提供了高带宽电路。 该电路可以包括组合电容器分离，电感树结构和各种带宽扩展技术的放大器，例如并联峰值，串联峰值和T形线圈峰值，以支持45Gbs / s及以上的数据速率，同时减少数据抖动。 电感树结构的电感元件还可以包括高阻抗传输线，从而简化了实现。 此外，电感器和t-线圈的容易识别的金属结构，负载电容器的相等分配以及对称的电感树结构可以简化收发器实现，但不限于时钟数据恢复电路。

公开(公告)号：US20140153680A1

公开(公告)日：2014-06-05

申请号：US13691482

申请日：2012-11-30

Applicant: BROADCOM CORPORATION

Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

IPC: H04L7/033

CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

公开(公告)号：US20130229232A1

公开(公告)日：2013-09-05

申请号：US13867883

申请日：2013-04-22

Applicant: BROADCOM CORPORATION

Inventor： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC: H03F3/16

CPC classification number: H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03F2203/45706

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

Abstract translation: 为高速收发器提供了高带宽电路。 该电路可以包括组合电容器分离，电感树结构和各种带宽扩展技术的放大器，例如并联峰值，串联峰值和T形线圈峰值，以支持45Gbs / s及以上的数据速率，同时减少数据抖动。 电感树结构的电感元件还可以包括高阻抗传输线，从而简化了实现。 此外，电感器和t-线圈的容易识别的金属结构，负载电容器的相等分配以及对称的电感树结构可以简化收发器实现，但不限于时钟数据恢复电路。

公开(公告)号：US09344268B1

公开(公告)日：2016-05-17

申请号：US14668165

申请日：2015-03-25

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Burak Catli ,  Wayne Wah-Yuen Wong ,  Kangmin Hu ,  Hyo Gyuem Rhew ,  Delong Cui ,  Jun Cao ,  Bo Zhang ,  Afshin Doctor Momtaz

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04J3/0685 ,  H04J3/047 ,  H04L7/0025

Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Abstract translation: 相位对准架构增强了通信系统的性能。 即使在非常高的速度下，分频时钟的分频时钟（例如，差分同相（I）和正交（Q））与主时钟对准，其中分频时钟的偏移变化与主时钟周期相当。 相位对准的改进有助于超高速通信。

公开(公告)号：US09136797B2

公开(公告)日：2015-09-15

申请号：US14042274

申请日：2013-09-30

Applicant: Broadcom Corporation

Inventor： Kuo-J Huang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz ,  Iuri Mehr ,  Ramon Alejandro Gomez

IPC: H03F3/45 ,  H03F1/32

CPC classification number: H03F1/3205 ,  H03F1/3211 ,  H03F1/3241 ,  Y10T29/49016

Abstract: Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

Abstract translation: 这里描述了利用负增益自适应地抑制放大器中的谐波失真的技术。 放大器包括并联耦合的第一放大级和第二放大级。 第一个放大器级具有正增益。 第二放大器级具有负增益以抑制包括放大器的系统的总谐波失真。 放大器还包括耦合到第一放大器级和第二放大器级的并联峰值电路，以增加放大器能够操作的最大工作频率。