A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided.