公开(公告)号：US11765980B2

公开(公告)日：2023-09-19

申请号：US17078630

申请日：2020-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Yung Ko ,  Chern-Yow Hsu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H10N50/01 ,  H10B61/00 ,  H10B63/00 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10B63/30 ,  H10N50/10 ,  H10N50/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

公开(公告)号：US11279615B2

公开(公告)日：2022-03-22

申请号：US16384066

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

IPC: B81C1/00 ,  B81B7/00 ,  H01L23/00

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

公开(公告)号：US20220069204A1

公开(公告)日：2022-03-03

申请号：US17078630

申请日：2020-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Yung Ko ,  Chern-Yow Hsu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L43/12 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L45/00

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

公开(公告)号：US10516026B2

公开(公告)日：2019-12-24

申请号：US16166603

申请日：2018-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.

公开(公告)号：US10510763B2

公开(公告)日：2019-12-17

申请号：US15607337

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC: H01L27/11521 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

公开(公告)号：US20190103256A1

公开(公告)日：2019-04-04

申请号：US15927308

申请日：2018-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Liao ,  Chang-Ming Wu ,  Lee-Chuan Tseng

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213 ,  C23C16/44

Abstract: In some embodiments, a method for cleaning a processing chamber is provided. The method may be performed by introducing a processing gas into a processing chamber that has a by-product disposed along sidewalls of the processing chamber. A plasma is generated from the processing gas using a radio frequency signal. A lower electrode is connected to a first electric potential. Concurrently, a bias voltage having a second electric potential is applied to a sidewall electrode to induce ion bombardment of the by-product, in which the second electric potential has a larger magnitude than the first electric potential. The processing gas is evacuated from the processing chamber.

公开(公告)号：US09865610B2

公开(公告)日：2018-01-09

申请号：US15438907

申请日：2017-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L27/11 ,  H01L27/115 ,  H01L27/11534 ,  H01L29/66 ,  H01L27/11521

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

公开(公告)号：US09673205B2

公开(公告)日：2017-06-06

申请号：US14834423

申请日：2015-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC: H01L27/115 ,  H01L27/11521 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32137 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

公开(公告)号：US09653471B2

公开(公告)日：2017-05-16

申请号：US15143811

申请日：2016-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/78 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/08

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US20170040429A1

公开(公告)日：2017-02-09

申请号：US15332115

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51 ,  H01L27/115

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a split gate memory device. In some embodiments, the split gate memory device includes a memory gate arranged over a substrate, and a select gate arranged over the substrate. An inter-gate dielectric layer is arranged between sidewalls of the memory gate and the select gate that face one another. The inter-gate dielectric layer extends under the memory gate. A first dielectric is disposed above the inter-gate dielectric layer and is arranged between the sidewalls of the memory gate and the select gate.

Abstract translation: 本公开涉及一种分离栅极存储器件。 在一些实施例中，分离栅极存储器件包括布置在衬底上的存储器栅极和布置在衬底上的选择栅极。 栅极间电介质层布置在存储器栅极的侧壁和彼此面对的选择栅极之间。 栅极间电介质层在存储栅下方延伸。 第一电介质设置在栅极间电介质层的上方，并且布置在存储栅极和选择栅极的侧壁之间。