Invention Application
- Patent Title: SUB-BLOCK ERASE
- Patent Title (中): 子块擦除
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Application No.: US14668790Application Date: 2015-03-25
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Publication No.: US20160049201A1Publication Date: 2016-02-18
- Inventor: Hang-Ting LUE , Kuo-Pin CHANG
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Main IPC: G11C16/14
- IPC: G11C16/14

Abstract:
A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.
Public/Granted literature
- US09620217B2 Sub-block erase Public/Granted day:2017-04-11
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