公开(公告)号：US20230009065A1

公开(公告)日：2023-01-12

申请号：US17368700

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4096 ,  G11C5/06

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20220246195A1

公开(公告)日：2022-08-04

申请号：US17321664

申请日：2021-05-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Kai HSU ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C11/408 ,  G11C11/4074 ,  G11C15/04 ,  G11C5/06 ,  H03K19/017

Abstract: A three-dimension (3D) memory device and an operation method thereof are provided. The 3D memory device includes: a memory array including a plurality of memory cells; a controller coupled to the memory array; and a match circuit coupled to memory array, wherein in data search and match, the controller selects from the memory cells a plurality of target memory cells sharing a same target global signal line, and the controller selects a plurality of target word lines sharing the target global signal line as a plurality of target search lines, wherein a search data sends to the target memory cells via the target search lines for data matching; the target global signal line is precharged; and outputting a match address based on whether a voltage on the target global signal line is pulled down or not.

公开(公告)号：US20220020761A1

公开(公告)日：2022-01-20

申请号：US16931598

申请日：2020-07-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.

公开(公告)号：US20200295031A1

公开(公告)日：2020-09-17

申请号：US16353028

申请日：2019-03-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/28 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311

Abstract: A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.

公开(公告)号：US20230317143A1

公开(公告)日：2023-10-05

申请号：US18206422

申请日：2023-06-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/10 ,  G11C16/28

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4099 ,  G11C16/102 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20230007890A1

公开(公告)日：2023-01-12

申请号：US17368705

申请日：2021-07-06

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Cheng-Lin SUNG ,  Yung-Feng LIN

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C16/10 ,  G11C16/28

Abstract: A memory device includes a high density or 3D data memory and a 3D reference memory. The reference memory is used to generate a reference signal used to sense data in the data memory. Conversion circuitry converts signals from one memory cell or a group of memory cells in the reference memory into a reference signal. The reference signal is applied to a sense amplifier to sense data stored in a selected memory cell in the data memory.

公开(公告)号：US20220246212A1

公开(公告)日：2022-08-04

申请号：US17475424

申请日：2021-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Po-Kai HSU

IPC: G11C16/04 ,  G11C16/08 ,  G06F7/544

Abstract: A memory device and an operation method thereof are provided. The operation method comprises: in performing a multiply accumulate (MAC) operation, inputting a plurality of inputs into a plurality of memory cells via a plurality of first signal lines; outputting a plurality of cell currents from the memory cells to a plurality of second signal lines based on a plurality of weights of the memory cells; summing the cell currents on each of the second signal lines into a plurality of signal line currents: summing the signal line currents into a global signal line current: and converting the global signal line current into an output, wherein the output represents a MAC operation result of the inputs and the weights.

公开(公告)号：US20220013180A1

公开(公告)日：2022-01-13

申请号：US17105669

申请日：2020-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tzu-Hsuan HSU ,  Po-Kai HSU ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C16/26 ,  G11C16/14

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.

公开(公告)号：US20210074725A1

公开(公告)日：2021-03-11

申请号：US16749806

申请日：2020-01-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: H01L27/11597 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78 ,  H01L27/11592 ,  G11C11/22

Abstract: A device based on 2T vertical ferroelectric memory cells includes a plurality of select gate lines in a first layer, and a plurality of word lines in a second layer, with a plurality of vertical channel structures disposed operably with the select gate lines and word lines. A vertical channel structure of a memory cell in the plurality is disposed orthogonally relative to a corresponding select gate line and a corresponding word line, and forms a channel for the vertical select transistor and the vertical ferroelectric memory transistor. Ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line. A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line. A NOR architecture memory uses the 2T vertical ferroelectric memory cells.

公开(公告)号：US20200026990A1

公开(公告)日：2020-01-23

申请号：US16172921

申请日：2018-10-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: G06N3/063 ,  G06F7/544 ,  H01L27/11578

Abstract: A neural network system for execution of a sum-of-products operation includes a memory device and a controller. The memory device includes a 3D array having a plurality of memory cells with programmable conductances disposed in cross-points of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductances for corresponding to weights of terms in the sum-of-products operation, a input driver used to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sensing circuit used to sense currents passing through the memory cells corresponding the terms in the sum-of-products operation, a buffer circuit used to store the terms. The controller is used to control the memory device summing up the terms in the sum-of-products operation.