Invention Application
US20160064371A1 NON-PLANAR ESD DEVICE FOR NON-PLANAR OUTPUT TRANSISTOR AND COMMON FABRICATION THEREOF
审中-公开
非平面输出晶体管非平面ESD器件及其普通制造
- Patent Title: NON-PLANAR ESD DEVICE FOR NON-PLANAR OUTPUT TRANSISTOR AND COMMON FABRICATION THEREOF
- Patent Title (中): 非平面输出晶体管非平面ESD器件及其普通制造
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Application No.: US14471712Application Date: 2014-08-28
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Publication No.: US20160064371A1Publication Date: 2016-03-03
- Inventor: Jian-Hsing LEE , Jagar SINGH , Manjunatha PRABHU , Anil KUMAR , Mahadeva Iyer NATARAJAN , Min-hwa CHI
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L21/8249 ; H01L27/06

Abstract:
Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT. Protecting the non-planar output transistors further includes electrically coupling the drain of the non-planar transistor and the collector of the BJT to an output of a circuit, and electrically coupling the source of the non-planar transistor, the emitter of the BJT and the well contact to a ground of the circuit.
Information query
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