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    DUAL THREE-DIMENSIONAL AND RF SEMICONDUCTOR DEVICES USING LOCAL SOI
    2.
    发明申请
    DUAL THREE-DIMENSIONAL AND RF SEMICONDUCTOR DEVICES USING LOCAL SOI 有权
    使用本地SOI的双三维和RF半导体器件

    公开(公告)号：US20160118414A1

    公开(公告)日：2016-04-28

    申请号：US14525842

    申请日：2014-10-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar SINGH ,  Srikanth Balaji SAMAVEDAM

    IPC: H01L27/12 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L23/66 ,  H01L21/84 ,  H01L21/3105

    CPC classification number: H01L27/1211 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/845 ,  H01L23/66 ,  H01L27/092 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s).

    Abstract translation: 具有三维半导体器件的射频（RF）半导体器件的共同制造包括提供起始三维半导体结构，起始结构包括体硅半导体衬底，耦合到衬底的凸起半导体结构 并被一层隔离材料包围。 在相邻的凸起结构之间的隔离材料层的跨度是凹进的，并且在隔离材料的凹陷跨度上形成一层外延半导体材料，在其上产生另一层隔离材料。 RF器件制造在外延材料上方的隔离材料层上，其产生局部绝缘体上硅，而三维半导体器件可以在凸起结构上制造。

    DIODE STRUCTURES
    5.
    发明申请
    DIODE STRUCTURES 审中-公开

    公开(公告)号：US20200328272A1

    公开(公告)日：2020-10-15

    申请号：US16382718

    申请日：2019-04-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jagar SINGH ,  Shiv Kumar MISHRA

    IPC: H01L29/06 ,  H01L27/06

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

    BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATION
    6.
    发明申请
    BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATION 有权

    公开(公告)号：US20160181393A1

    公开(公告)日：2016-06-23

    申请号：US15057791

    申请日：2016-03-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar SINGH

    IPC: H01L29/66

    CPC classification number: H01L29/66325 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7393

    Abstract: A structure, including a bipolar junction transistor and method of fabrication thereof, is provided herein. The bipolar junction transistor includes: a substrate including a substrate region having a first conductivity type; an emitter region over a first portion of the substrate region, the emitter region having a second conductivity type; a collector region over a second portion of the substrate region, the collector region having the second conductivity type; and, a base region overlie structure disposed over, in part, the substrate region. The base region overlie structure separates the emitter region from the collector region and aligns to a base region of the bipolar junction transistor within the substrate region, between the first portion and the second portion of the substrate region.

    NON-PLANAR SCHOTTKY DIODE AND METHOD OF FABRICATION
    7.
    发明申请
    NON-PLANAR SCHOTTKY DIODE AND METHOD OF FABRICATION 有权
    非平面肖特基二极管和制造方法

    公开(公告)号：US20160118473A1

    公开(公告)日：2016-04-28

    申请号：US14525744

    申请日：2014-10-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar SINGH ,  Jerome CIAVATTI

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/872

    CPC classification number: H01L29/66143 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/872

    Abstract: A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs.

    Abstract translation: 非平面肖特基二极管包括第一类型的半导体衬底，第一类型包括n型和p型之一。 该结构还包括与耦合到衬底的第一类型相反的第二类型的凸起半导体结构，围绕凸起结构的下部的隔离材料，直立在凸起结构下方的第二类型的第一阱（ s），围绕第一阱的顶部的边缘的第一类型的保护环，在隔离材料上方的凸起结构的顶部上的硅化物的保形层，以及在保形层之上的公共接触 硅化物层。 非平面肖特基二极管可以用非平面晶体管制造，例如FinFET。

    METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES
    8.
    发明申请
    METHOD FOR MAKING HIGH VOLTAGE INTEGRATED CIRCUIT DEVICES IN A FIN-TYPE PROCESS AND RESULTING DEVICES 有权
    用于在FIN型工艺和结晶器件中制造高电压集成电路器件的方法

    公开(公告)号：US20160111422A1

    公开(公告)日：2016-04-21

    申请号：US14965193

    申请日：2015-12-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jagar SINGH

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165

    CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

    Abstract: Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.

    Abstract translation: 公开了利用鳍式工艺制造高压IC器件和所得器件的方法。 实施例包括在衬底层上形成由空间隔开的两个多个硅散热片，其中相邻的硅散热片被沟槽分开; 在衬底层上形成氧化物层并填充每个沟槽的一部分; 形成两个深的隔离沟槽到与两个多个硅散热片相邻的氧化物层和衬底层; 通过将掺杂剂注入到两个多个硅散热片下面的衬底层中来形成渐变电压结; 在所述氧化物层和所述两个硅散热片之间形成栅极结构; 将掺杂剂注入到两个多个硅散热片之中和之下，形成源区和漏区; 并在两个多个硅散热片上形成外延层以形成合并的源极和漏极散热片。

    METHODS OF FABRICATING NANOWIRE STRUCTURES
    9.
    发明申请
    METHODS OF FABRICATING NANOWIRE STRUCTURES 有权
    制备纳米结构的方法

    公开(公告)号：US20160225849A1

    公开(公告)日：2016-08-04

    申请号：US14613983

    申请日：2015-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chun Yu WONG ,  Min-hwa CHI ,  Ashish BARASKAR ,  Jagar SINGH

    IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02

    CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78696

    Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

    Abstract translation: 提出了用于制造纳米线结构的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括例如：提供衬底并在衬底上形成翅片，使得翅片具有包括一个或多个细长的第一侧壁突出部的第一侧壁和包括一个或多个细长的第二侧壁突出部的第二侧壁， 更细长的第二侧壁突起基本上与一个或多个细长的第一侧壁突起对准; 并且用细长的第一侧壁突起和细长的第二侧壁突起各向异性地蚀刻翅片以限定一个或多个纳米线。 可以选择蚀刻剂以沿着预定义的结晶平面（例如（111）晶面）选择性地蚀刻，以形成纳米线结构。

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